Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package

Patent metadata

Field	Value
Publication number	US-9318404-B2
Application number	US-201313759911-A
Country	US
Kind code	B2
Filing date	Feb 5, 2013
Priority date	Feb 5, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.

First claim

What is claimed:

1. A semiconductor device, comprising:
a semiconductor die;
an encapsulant disposed over the semiconductor die and physically contacting a first surface of the semiconductor die;
an interconnect structure formed over a first surface of the encapsulant and over an active surface of the semiconductor die opposite the first surface of the semiconductor die; and
a plurality of vias formed partially through a second surface of the encapsulant opposite the first surface of the encapsulant with a portion of the encapsulant remaining between the vias and the first surface of the encapsulant, wherein a first area of the second surface of the encapsulant at a corner of the semiconductor device includes a greater number of the vias than a second area of the second surface of the encapsulant equal in size to the first area, the second area extending from a side surface of the semiconductor die to an edge of the semiconductor device.

2. The semiconductor device of claim 1 , wherein a depth of the vias is greater than a distance between the first surface of the semiconductor die and the second surface of the encapsulant.

3. The semiconductor device of claim 1 , wherein a depth of a first via of the plurality of vias is different from a depth of a second via of the plurality of vias.

4. The semiconductor device of claim 1 , wherein a diameter of a first via of the plurality of vias is 100-500 micrometers.

5. The semiconductor device of claim 1 , wherein a diameter of a first via of the plurality of vias is different from a diameter of a second via of the plurality of vias.

6. A semiconductor device, comprising:
a semiconductor die;
an encapsulant disposed around the semiconductor die;
a plurality of vias formed through a first surface of the encapsulant with a first portion of the encapsulant remaining between the vias and a second surface of the encapsulant opposite the first surface of the encapsulant, wherein a first area of the encapsulant at a corner of the semiconductor device includes a greater number of the vias than a second area of the encapsulant equal in size to the first area and located between a side surface of the semiconductor die and an edge of the semiconductor device; and
a conductive layer formed over the second surface of the encapsulant and a first surface of the semiconductor die.

7. The semiconductor device of claim 6 , wherein:
a second portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface of the semiconductor die; and
a depth of the vias is greater than a thickness of the second portion of the encapsulant.

8. The semiconductor device of claim 6 , wherein:
a depth (Dl) of the vias is less than a distance (D 2 ) extending from the first surface of the encapsulant to the second surface of the encapsulant; and
a ratio of Dl:D 2 is less than or equal to 4:5.

9. The semiconductor device of claim 6 , further including a repair material disposed within the vias.

10. The semiconductor device of claim 9 , wherein a surface of the repair material is recessed below or coplanar with the first surface of the encapsulant.

11. The semiconductor device of claim 6 , further including a support layer comprising an insulating material disposed over the semiconductor die and encapsulant.

12. The semiconductor device of claim 11 , wherein the vias are formed through the support layer.

13. A semiconductor device, comprising:
a semiconductor die;
an encapsulant disposed around the semiconductor die;
a plurality of vias formed in a first surface of the encapsulant with a first portion of the encapsulant disposed between the vias and a second surface of the encapsulant opposite the first surface of the encapsulant; and
a repair material disposed in the vias and physically contacting the encapsulant along a sidewall of the vias.

14. The semiconductor device of claim 13 , further including an interconnect structure formed over the semiconductor die and encapsulant.

15. The semiconductor device of claim 13 , wherein the vias are formed in a row offset from a side surface of the semiconductor die.

16. The semiconductor device of claim 13 , wherein a surface of the repair material is coplanar with or recessed below the first surface of the encapsulant.

17. The semiconductor device of claim 13 , further including a support layer comprising an insulating material disposed over the semiconductor die and encapsulant.

18. The semiconductor device of claim 17 , wherein the vias are formed through the support layer.

19. The semiconductor device of claim 13 , wherein a density of a first group of the vias at a corner of the semiconductor device is greater than a density of a second group of the vias offset from a side surface of the semiconductor die.

20. The semiconductor device of claim 13 , wherein the vias are formed offset from a corner of the semiconductor die.

21. The semiconductor device of claim 13 , wherein a second portion of the encapsulant is disposed over a surface of the semiconductor die and a depth of the vias is greater than a distance between the surface of the semiconductor die and the first surface of the encapsulant.

Assignees

• Stats Chippac Ltd

Inventors

• Lin Yaojian
• Marimuthu Pandi Chelvam
• Chen Kang
• GU Yu

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title