Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-2018138118-A1
Application number	US-201715813866-A
Country	US
Kind code	A1
Filing date	Nov 15, 2017
Priority date	Oct 16, 2013
Publication date	May 17, 2018
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A method of forming an integrated circuit (IC) package substrate comprising:
depositing a first lamination layer on a first side of the package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate, wherein the first side is disposed opposite the second side and the first lamination layer is to prevent deposition of the first surface finish on one or more electrical contacts disposed on the first side; removing the first lamination layer from the first side of the package substrate to expose the one or more electrical contacts disposed on the first side; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate, wherein the second lamination layer is to prevent deposition of the second surface finish on the one or more electrical contacts disposed on the second side; and removing the second lamination layer from the second side of the package substrate.

2 . The method of claim 1 , wherein the depositing of the first surface finish is accomplished by a Direct Immersion Gold (DIG) process and the one or more electrical contacts disposed on the second side include die bond pads.

3 . The method of claim 1 , wherein the depositing of the first surface finish is accomplished by an Electroless Palladium Immersion Gold (EPIG) process and the one or more electrical contacts disposed on the second side include die bond pads.

4 . The method of claim 1 , wherein the depositing of the first surface finish is accomplished by an Organic Solderability Preservative (OSP) process and the one or more electrical contacts disposed on the second side include die bond pads.

5 . The method of claim 1 , wherein depositing the second surface finish is accomplished using an electroless plating process and the one or more electrical contacts disposed on the second side include one or more lands.

6 . The method of claim 1 , wherein depositing the second surface finish includes depositing nickel (Ni) and the one or more electrical contacts disposed on the second side include one or more lands.

7 . The method of claim 6 , wherein depositing the second surface finish includes depositing one or both of palladium or gold.

8 . The method of claim 7 , wherein depositing the second surface finish includes depositing gold using an electroless nickel-immersion gold (ENIG+EG) process.

9 . The method of claim 1 , wherein depositing the second surface finish includes depositing imidazole or an imidazole derivative.

10 . The method of claim 1 , wherein, after deposition, the second surface finish has a thickness of less than or equal to 500 nanometers.

11 . The method of claim 1 , wherein depositing the first surface finish includes depositing nickel (Ni).

12 . The method of claim 1 , wherein depositing the first surface finish includes depositing one or both of palladium or gold.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei
• Lotz Stefanie M

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title