Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2018130786-A1
Application number	US-201715635615-A
Country	US
Kind code	A1
Filing date	Jun 28, 2017
Priority date	Nov 9, 2016
Publication date	May 10, 2018
Grant date	—

Abstract

A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

First claim

1 . A semiconductor device comprising:
a first active pattern extending in a first direction on a first region and a second region of a substrate; a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region; a contact structure contacting the first dummy gate electrode and extending in the first direction; and a power line disposed on the contact structure and electrically connected to the contact structure, the power line extending in the first direction, wherein the contact structure overlaps the power line when viewed in a plan view.

2 . The semiconductor device of claim 1 , wherein the contact structure comprises:
a linear portion having a linear shape extending in the first direction; and a first protruding portion protruding from the linear portion in the second direction.

3 . The semiconductor device of claim 2 , wherein the linear portion and the first protruding portion are spaced apart from the first active pattern when viewed in a plan view.

4 . (canceled)

5 . The semiconductor device of claim 2 , wherein the contact structure further comprises: a second protruding portion protruding from the linear portion in the second direction, and
wherein the second protruding portion is electrically connected to a source/drain region of the first active pattern.

6 . The semiconductor device of claim 5 , wherein a height of a bottom surface of the second protruding portion in a direction perpendicular to a top surface of the substrate is different from a height of a bottom surface of the linear portion in the direction perpendicular to the top surface of the substrate.

7 . The semiconductor device of claim 1 , further comprising:
a via disposed between the contact structure and the power line and extending in the first direction.

8 . The semiconductor device of claim 1 , wherein the first dummy gate electrode prevents carriers from moving between the first region and the second region in the first active pattern.

9 . The semiconductor device of claim 1 , further comprising:
a gate electrode crossing the first active pattern and extending in the second direction, wherein the gate electrode is spaced apart from the contact structure.

10 . The semiconductor device of claim 1 , further comprising:
a device isolation pattern disposed on the substrate and defining the first active pattern, wherein the contact structure overlaps the device isolation pattern when viewed in a plan view.

11 . (canceled)

12 . The semiconductor device of claim 1 , further comprising:
a second active pattern extending in the first direction on a third region and a fourth region of the substrate, wherein the first dummy gate electrode crosses the second active pattern, and wherein the contact structure is provided between the first region and the third region and between the second region and the fourth region.

13 - 18 . (canceled)

19 . A semiconductor device comprising:
a first standard cell, a second standard cell, a third standard cell and a fourth standard cell provided on a substrate; a first dummy gate electrode provided at a boundary between the first standard cell and the second standard cell; a contact structure provided at a boundary between the first standard cell and the third standard cell and a boundary between the second standard cell and the fourth standard cell; and a power line provided at the boundary between the first standard cell and the third standard cell and the boundary between the second standard cell and the fourth standard cell, wherein the first standard cell and the second standard cell are arranged in a first direction, wherein the third standard cell and the fourth standard cell are arranged in the first direction, wherein the first standard cell and the third standard cell are arranged in a second direction crossing the first direction, wherein the second standard cell and the fourth standard cell are arranged in the second direction, and wherein the power line applies a voltage to the first dummy gate electrode through the contact structure.

20 . The semiconductor device of claim 19 , wherein the first dummy gate electrode electrically isolates the first standard cell and the second standard cell from each other.

21 . The semiconductor device of claim 19 , wherein each of the first standard cell, the second standard cell, the third standard cell, and the fourth standard cell includes logic transistors constituting a logic circuit.

22 . The semiconductor device of claim 19 , wherein the first dummy gate electrode extends from the boundary between the first standard cell and the second standard cell to a boundary between the third standard cell and the fourth standard cell.

23 . The semiconductor device of claim 19 , further comprising:
a second dummy gate electrode provided at a boundary between the third standard cell and the fourth standard cell, wherein the power line applies the voltage to the second dummy gate electrode through the contact structure.

24 - 25 . (canceled)

26 . A semiconductor device comprising:
an active pattern provided on a substrate extending in a first direction, the active pattern having a pair of source/drain regions and a depletion region between the pair of source/drain regions; a dummy gate electrode on the depletion region and extending in a second direction crossing the active pattern; a contact structure disposed on the dummy gate electrode and connected to the dummy gate electrode and extending in the first direction; and a via and a power line disposed on the contact structure, wherein the via is disposed between the contact structure and the power line, the via having a linear shape extending in the first direction and the power line having a linear shape extending along the via in the first direction, wherein the contact structure and the via overlap the power line when viewed in a plan view.

27 . The semiconductor device of claim 26 , wherein a longitudinal direction of the power line is the first direction.

28 . The semiconductor device of claim 26 , wherein a width of the power line in the second direction is greater than a width of the via in the second direction.

29 . The semiconductor device of claim 26 , wherein a width of the power line in the second direction is greater than a width of the contact structure in the second direction.

30 . The semiconductor device of claim 26 , wherein the power line and the via are integrally formed to constitute one body.

31 - 40 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Deepak Sharma
• Ranjan Rajeev
• Subhash Kuchanuri
• Park Chulhong
• Yang Jaeseok
• Chun Kwanyoung

Classifications

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/42372

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic