Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9947661-B2
Application number	US-201715641417-A
Country	US
Kind code	B2
Filing date	Jul 5, 2017
Priority date	Oct 1, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first active pattern and a second active pattern spaced apart from each other in a first direction, the first and second active patterns protruding upwardly from the substrate;
a device isolation layer between the first active pattern and the second active pattern on the substrate, wherein an uppermost surface of the device isolation layer is at a height below an uppermost surface of each of the first and second active patterns;
a first gate structure and a second gate structure crossing the first active pattern and the second active pattern, respectively, and extending in a second direction intersecting the first direction;
a dummy gate structure between the first gate structure and the second gate structure, the dummy gate structure extending in the second direction on the device isolation layer;
a first source/drain region on the first active pattern between the first gate structure and the dummy gate structure;
a second source/drain region on the second active pattern between the second gate structure and the dummy gate structure;
a connection contact on the dummy gate structure, the connection contact extending in the first direction to connect the first source/drain region to the second source/drain region; and
a common conductive line on the connection contact, the common conductive line electrically connected to the first and second source/drain regions via the connection contact.

2. The semiconductor device of claim 1 , wherein a lowermost surface of the dummy gate structure is at a height below the uppermost surface of each of the first and second active pattern.

3. The semiconductor device of claim 2 , wherein the dummy gate structure includes a gate insulating pattern, a dummy gate pattern, and a capping pattern sequentially stacked on the device isolation layer, and the gate insulating pattern of the dummy gate structure is in contact with the uppermost surface of the device isolation layer.

4. The semiconductor device of claim 2 , wherein the lowermost surface of the dummy gate structure is at a height below an uppermost surface of each of the first and second source/drain regions.

5. The semiconductor device of claim 1 , wherein the dummy gate structure is spaced apart from at least one of the first and second source/drain regions.

6. The semiconductor device of claim 1 , wherein a lowermost surface of the dummy gate structure is at a height below a lowermost surface of each of the first and second gate structures.

7. The semiconductor device of claim 6 , wherein an uppermost surface of the dummy gate structure is at the same height as that of an uppermost surface of each of the first and second gate structures, from the substrate.

8. The semiconductor device of claim 1 , wherein the device isolation layer is a first device isolation layer,
the device further comprising:
second device isolation layers spaced apart from each other in the second direction with each of the first and second active patterns interposed therebetween,
wherein the second device isolation layers expose sidewalls of each of the first and second active patterns, and each of the first and second gate structures covers the sidewalls of a corresponding one of the first and second active patterns.

9. The semiconductor device of claim 1 , wherein each of the first gate structure, the second gate structure, and the dummy gate structure include a gate insulating pattern, and
wherein the gate insulating pattern of the dummy gate structure is in contact with the uppermost surface of the device isolation layer, and the gate insulating pattern of each of the first and second gate structures is in contact with the uppermost surface of a corresponding one of the first and second active patterns.

10. The semiconductor device of claim 1 , wherein
the connection contact comprises:
a horizontal extension extending in the first direction; and
vertical extensions extending from the horizontal extension to the first and second source/drain regions, respectively, and

bottom surfaces of the vertical extensions are in contact with the first and second source/drain regions, respectively.

11. A semiconductor device, comprising:
a first active pattern and a second active pattern spaced apart from each other in a first direction, the first and second active patterns protruding upwardly from the substrate;
a device isolation layer between the first active pattern and the second active pattern on the substrate;
a first gate structure and a second gate structure crossing the first active pattern and the second active pattern, respectively, and extending in a second direction intersecting the first direction;
a dummy gate structure between the first gate structure and the second gate structure, the dummy gate structure extending in the second direction on the device isolation layer, wherein a lowermost surface of the dummy gate structure is at a height below an uppermost surface of each of the first and second active patterns;
a first source/drain region on the first active pattern between the first gate structure and the dummy gate structure;
a second source/drain region on the second active pattern between the second gate structure and the dummy gate structure;
a connection contact on the dummy gate structure, the connection contact extending in the first direction to connect the first source/drain region to the second source/drain region; and
a common conductive line on the connection contact, the common conductive line electrically connected to the first and second source/drain regions via the connection contact.

12. The semiconductor device of claim 11 , wherein the lowermost surface of the dummy gate structure is at a height below an uppermost surface of each of the first and second source/drain regions.

13. The semiconductor device of claim 12 , wherein the dummy gate structure is spaced apart from at least one of the first and second source/drain regions.

14. The semiconductor device of claim 11 , wherein the lowermost surface of the dummy gate structure is at a height below lowermost surface of each of the first and second gate structures.

15. The semiconductor device of claim 14 , wherein the dummy gate structure include the same material as each of the first and second gate structures.

16. The semiconductor device of claim 14 , wherein an uppermost surface of the dummy gate structure is at the same height as that of an uppermost surface of each of the first and second gate structures, from the substrate.

17. The semiconductor device of claim 11 , wherein
the connection contact comprises:
a horizontal extension extending in the first direction; and
vertical extensions extending from the horizontal extension to the first and second source/drain regions, respectively, and

the horizontal extension is in contact with an uppermost surface of the dummy gate structure.

18. The semiconductor device of claim 17 , wherein at least one of the vertical extensions is in contact with a side surface of the dummy gate structure.

19. The semiconductor device of claim 17 , wherein the dummy gate structure includes a dummy gate pattern, and gate spacers on both side surfaces of the dummy gate pattern, and
wherein each of the gate spacers is between the dummy gate pattern and each of the vertical extensions.

20. The semiconductor device of claim 17 , wherein the lowermost surface of the dummy gate structure is at the same height as that of an uppermost surface of the devic

Assignees

• Samsung Electronics Co Ltd

Inventors

• Azmat Raheel
• Deepak Sharma
• Park Chulhong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L2027/11829

  Electricity · mapped topic