Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9418990-B2
Application number	US-201514736441-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Oct 1, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first gate structure and a second gate structure extending in a first direction and spaced apart from each other in a second direction intersecting the first direction;
a dummy gate structure between the first gate structure and the second gate structure, the dummy gate structure extending in the first direction;
a first source/drain region between the first gate structure and the dummy gate structure;
a second source/drain region between the second gate structure and the dummy gate structure;
a connection contact on the dummy gate structure, the connection contact extending in the second direction to connect the first source/drain region to the second source/drain region; and
a common conductive line on the connection contact, the common conductive line configured to apply a voltage to the first and second source/drain regions through the connection contact.

2. The semiconductor device of claim 1 , wherein
the connection contact comprises:
a horizontal extension extending in the second direction; and
vertical extensions extending from the horizontal extension to top surfaces of the first and second source/drain regions, respectively, and

bottom surfaces of the vertical extensions are in contact with the first and second source/drain regions, respectively.

3. The semiconductor device of claim 2 , wherein a bottom surface of the horizontal extension is in contact with a top surface of the dummy gate structure.

4. The semiconductor device of claim 1 , further comprising:
a via-contact between the connection contact and the common conductive line,
the common conductive line for applying the same voltage to the first and second source/drain regions through the via-contact and the connection contact.

5. The semiconductor device of claim 1 , further comprising:
a third source/drain region between the first gate structure and the dummy gate structure, the third source/drain region being spaced apart from the first source/drain region in the first direction;
a fourth source/drain region between the second gate structure and the dummy gate structure, the fourth source/drain region being spaced apart from the second source/drain region in the first direction;
a first contact between the first gate structure and the dummy gate structure, the first contact being in contact with the third source/drain region; and
a second contact between the second gate structure and the dummy gate structure, the second contact being in contact with the fourth source/drain region,
top surfaces of the first and second contacts being at a substantially same level as a top surface of the connection contact.

6. The semiconductor device of claim 5 , wherein the first contact, the second contact, and the connection contact include identical materials.

7. The semiconductor device of claim 5 , wherein
the first and second contacts have bar shapes extending in the first direction, and
the first and second contacts are spaced apart from the connection contact in the first direction.

8. The semiconductor device of claim 5 , wherein
each of the first contact, the second contact, and the connection contact has a width in the second direction, and
the width of the connection contact is greater than the widths of the first and second contacts.

9. A semiconductor device, comprising:
a dummy gate structure on a substrate, the dummy gate structure extending in a first direction;
a first pair of transistors at respective opposing sides of the dummy gate structure;
a second pair of transistors at the respective opposing sides, the second pair of transistors being adjacent to the first pair of transistors in the first direction;
a connection contact on a top surface of the dummy gate structure, the connection contact extending along both sidewalls of the dummy gate structure so as to be connected in common to the first pair of transistors; and
a first contact and a second contact at the respective opposing sides, the first and second contacts connected to the second pair of transistors, respectively,
top surfaces of the first and second contacts being at a substantially same level as a top surface of the connection contact.

10. The semiconductor device of claim 9 , further comprising:
a plurality of logic cells on the substrate, the plurality of logic cells including,
a first logic cell, and
a second logic cell spaced apart from the first logic cell in the first direction,

the dummy gate structure intersecting the first logic cell and the second logic cell,
the first logic cell including the first pair of transistors, and
the second logic cell including the second pair of transistors.

11. The semiconductor device of claim 10 , further comprising:
a via-contact in contact with the top surface of the connection contact; and
a common conductive line in contact with a top surface of the via-contact,
the common conductive line configured to apply a drain voltage or a source voltage to the first pair of transistors through the via-contact and the connection contact.

12. The semiconductor device of claim 9 , further comprising:
a plurality of logic cells on the substrate, the plurality of logic cells including,
a first logic cell,
a second logic cell spaced apart from a first logic cell in a second direction,
a third logic cell spaced apart from the first logic cell in the first direction, and
a fourth logic cell spaced apart from the second logic cell in the first direction,

the dummy gate structure being between the first logic cell and the second logic cell and between the third logic cell and the fourth logic cell,
the first pair of transistors including a first transistor in the first logic cell, and a second transistor in the second logic cell, and
the second pair of transistors including a third transistor in the third logic cell, and a fourth transistor in the fourth logic cell.

13. The semiconductor device of claim 12 , further comprising:
a via-contact in contact with the top surface of the connection contact; and
a common conductive line in contact with a top surface of the via-contact,
the common conductive line being shared by the first logic cell and the second logic cell.

14. The semiconductor device of claim 13 , wherein the common conductive line applies the same voltage to the first and second transistors through the via-contact and the connection contact.

15. The semiconductor device of claim 9 , wherein the first contact, the second contact, and the connection contact include identical materials.

16. A semiconductor device, comprising:
first and second gate structures extending in a first direction,
the first gate structure being electrically connected to a first source/drain region and a second source/drain region, and
the second gate structure being electrically connected to a third source/drain region and a fourth source/drain region; and
a connection contact electrically connecting the first source/drain region to the third source/drain region, the connection contact extending in the first direction.

17. The semiconductor device of claim 16 , further comprising:
a dummy gate structure interposed between the first and third source/drain regions, and between the second and fourth source/drain regions,
the dummy gate structure extending in the first direction,
the connection contact traversing the dummy gate structure along a second direction, and
the second direction being substantially perpendicular to the first direction.

18. The semicon

Assignees

• Samsung Electronics Co Ltd

Inventors

• Azmat Raheel
• Deepak Sharma
• Park Chulhong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/797 Primary

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D84/975

  Wiring regions or routing · CPC title