Wafer stacking to form a multi-wafer-bonded structure

Patent metadata

Field	Value
Publication number	US-2018096833-A1
Application number	US-201715820839-A
Country	US
Kind code	A1
Filing date	Nov 22, 2017
Priority date	Sep 7, 2016
Publication date	Apr 5, 2018
Grant date	—

Abstract

In one aspect, a method includes heating a wafer chuck, heating a first wafer, depositing a first epoxy along at least a portion of a surface of the first wafer disposed on the wafer chuck, spinning the wafer chuck to spread the first epoxy at least partially across the first wafer, placing a second wafer on the first epoxy disposed on the first wafer and bonding the second wafer to the first epoxy under vacuum to form a two-wafer-bonded structure.

First claim

What is claimed is:

1 . A method, comprising:
heating a wafer chuck; heating a first wafer; depositing a first epoxy along at least a portion of a surface of the first wafer disposed on the wafer chuck; spinning the wafer chuck to spread the first epoxy at least partially across the first wafer; placing a second wafer on the first epoxy disposed on the first wafer; and bonding the second wafer to the first epoxy under vacuum to form a two-wafer-bonded structure.

2 . The method of claim 1 , further comprising:
heating a third wafer; depositing a second epoxy along at least a portion of a surface of the third wafer disposed on the wafer chuck; spinning the wafer chuck to spread the second epoxy at least partially across the third wafer; placing the second epoxy applied on the third wafer in contact with the first wafer of the two-wafer-bonded structure; and bonding the second epoxy to the first wafer under vacuum to form a three-wafer-bonded structure.

3 . The method of claim 2 , further comprising reheating the wafer chuck to at least 65° C.

4 . The method of claim 2 , wherein heating the third wafer comprises heating the third wafer to at least 65° C.

5 . The method of claim 2 , wherein heating the third wafer comprises heating a silicon wafer.

6 . The method of claim 2 , wherein the three-wafer-bonded structure is heated to cure the first epoxy and the second epoxy.

7 . The method of claim 1 , wherein depositing the second epoxy along at least a portion of a surface of the third wafer disposed on the wafer chuck comprises depositing the second epoxy while the wafer chuck is spinning at a first speed, and
wherein spinning the wafer chuck to spread the second epoxy at least partially across the third wafer comprises increasing a speed of the wafer chuck from the first speed to a second speed.

8 . The method of claim 1 , wherein depositing the second epoxy comprises depositing a second epoxy comprising material used in the first epoxy.

9 . The method of claim 1 , wherein heating the wafer chuck comprises heating the wafer chuck to at least 65° C.

10 . The method of claim 1 , wherein heating the first wafer comprises heating a first wafer to at least 65° C.

11 . The method of claim 1 , wherein heating the first wafer comprises heating one of a controlled expansion (CE) wafer, a stainless steel wafer or a titanium wafer.

12 . The method of claim 1 , wherein placing the second wafer on the first epoxy comprises placing a readout integrated circuit (ROIC) wafer on the first epoxy.

13 . The method of claim 12 , wherein placing the ROIC wafer comprises placing an ROIC wafer comprising indium bumps.

14 . The method of claim 1 , wherein depositing the first epoxy along at least a portion of a surface of the first wafer disposed on the wafer chuck comprises depositing the first epoxy while the wafer chuck is spinning at a first speed.

15 . The method of claim 14 , wherein spinning the wafer chuck to spread the first epoxy across the first wafer comprises increasing a speed of the wafer chuck from the first speed to a second speed.

16 . A multi-wafer-bonded stack, comprising:
a first wafer; and a second wafer bonded to the first wafer by a first epoxy, wherein the first epoxy is free of voids.

17 . The multi-wafer-bonded stack of claim 16 , further comprising a third wafer bonded to the first wafer by a second epoxy,
wherein the second epoxy is free of voids.

18 . The multi-wafer-bonded stack of claim 17 , wherein the first wafer is one of a controlled expansion (CE) wafer, a stainless steel wafer or a titanium wafer, and
wherein the second wafer is a readout integrated circuit (ROIC) wafer.

19 . The multi-wafer-bonded stack of claim 18 , wherein the third wafer is silicon.

20 . The multi-wafer-bonded stack of claim 18 , wherein the ROIC wafer comprises indium bumps.

Assignees

• Raytheon Co

Inventors

• Cahill Andrew
• Getty Jonathan
• Lofgreen Daniel D
• Drake Paul A

Classifications

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/0442 Primary

  Apparatus for placing on an insulating substrate, e.g. tape · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P14/6342 Primary

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10P10/128

  by direct semiconductor to semiconductor bonding · CPC title