Circuit and Method for Processing Data

Patent metadata

Field	Value
Publication number	US-2017366334-A1
Application number	US-201715616549-A
Country	US
Kind code	A1
Filing date	Jun 7, 2017
Priority date	Jun 21, 2016
Publication date	Dec 21, 2017
Grant date	—

Abstract

Systems and methods for processing data including a first and second component are described. An example circuit includes a processing stage arranged to calculate absolute values of the first component and the second component, and to output, at a first output, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output, a minimum value of the absolute value of the first component and the absolute value of the second component. The circuit includes a processing stage arranged to output, in response to the maximum value being greater than the minimum value times four, a value corresponding to the maximum value, and to output, in response to the maximum value being smaller than the minimum value times four, a value corresponding to a sum of seven times the maximum value and four times the minimum value.

First claim

What is claimed is:

1 . A circuit for processing data including a first component and a second component, the circuit comprising:
a first processing stage arranged to calculate an absolute value of the first component and an absolute value of the second component, and to output, at a first output of the first processing stage, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output of the first processing stage, a minimum value of the absolute value of the first component and the absolute value of the second component; and a second processing stage arranged to output, in response to the maximum value being greater than the minimum value times four, a value corresponding to the maximum value, and to output, in response to the maximum value being smaller than the minimum value times four, a value corresponding to a sum of seven times the maximum value and four times the minimum value.

2 . The circuit according to claim 1 , wherein the second processing stage includes a first output and a second output, and wherein the second processing stage is arranged to:
in response to the maximum value being greater than the minimum value times four, output at the first output a value corresponding to the maximum value, and to output at the second output a value corresponding to the minimum value, and in response to the maximum value being smaller than the minimum value times four, output at the first output a value corresponding to a sum of seven times the maximum value and four times the minimum value, and to output at the second output a value corresponding to a difference between seven times the minimum value and four times the maximum value.

3 . The circuit according to claim 2 , further comprising a mapping stage arranged to output a phase value selected from a plurality of predetermined phase values based on a value output at the first output of the second processing stage and a value output at the second output of the second processing stage.

4 . The circuit according to claim 3 , wherein the mapping stage is further arranged to calculate a first comparison value corresponding to a difference between the value output at the first output of the second processing stage and a product of an absolute value of the value output at the second output of the second processing stage and four, and to calculate a second comparison value corresponding to an absolute value of the value output at the second output of the second processing stage,
wherein the mapping stage is arranged to select the phase value based on an evaluation of a set of comparisons between the first comparison value and the second comparison value.

5 . The circuit according to claim 3 , further comprising a phase estimator stage arranged to output a phase estimate representing an estimate of a phase of the data including the first and the second component, the phase estimate being based on the phase value output by the mapping stage, information indicating an octant of the data, and information indicating whether the maximum value exceeds the minimum value times four.

6 . The circuit according to claim 5 , wherein the first processing stage is arranged to determine the octant based on the data and to output information regarding a result of the determination.

7 . The circuit according to claim 5 , wherein the second processing stage is arranged to determine whether the maximum value exceeds the minimum value times four and to output information regarding a result of the determination.

8 . The circuit according to claim 1 , wherein the second processing stage includes:
first calculation circuitry having a first input connected to the first output of the first processing stage, the first calculation circuitry being arranged to multiply a value received at the first input by eight, or a multiple of eight, and to output, at a first output of the second processing stage, a sum of the multiplied value and a value received at a second input of the first calculation circuitry, second calculation circuitry having a first input connected to the second output of the first processing stage and a second input connected to the first output of the first processing stage, the second calculation circuitry being arranged to multiply a value received at the first input by four, or a multiple of four, and to output, to the second input of the first calculation circuitry, a difference between the multiplied value and a value, or a multiple of the value, received at the second input of the second calculation circuitry, in response to the maximum value being smaller than the minimum value times four.

9 . The circuit according to claim 1 , wherein the second processing stage further includes:
third calculation circuitry having a first input connected to the second output of the first processing stage, the third calculation circuitry being arranged to multiply a value received at the first input of the third calculation circuitry by eight, or a multiple of eight, and to output, at a second output of the second processing stage, a difference between the multiplied value and a value received at a second input of the third calculation circuitry; and fourth calculation circuitry having a first input connected to the first output of the first processing stage and a second input connected to the second output of the first processing stage, the fourth calculation circuitry being arranged to multiply a value received at the first input of the second calculation circuitry by four, or by a multiple of four, and to output, to the second input of the third calculation circuitry, a sum of the multiplied value and a value, or a multiple of the value, received at the second input of the fourth calculation circuitry, in response to the maximum value being smaller than the minimum value times four.

10 . The circuit according to claim 1 , further comprising a magnitude estimator stage arranged to output a magnitude estimate representing an estimate of a magnitude of the data, the magnitude estimate being based on a value output by a first output of the second processing stage.

11 . A circuit according to claim 10 , wherein the magnitude estimator stage is further arranged to calculate the magnitude estimate based on at least one of:
an absolute value of a value output at a second output of the second processing stage, information indicating whether the maximum value exceeds the minimum value times four, a first comparison value corresponding to a difference between the value output at the first output of the second processing stage and a product of the absolute value and four, and on a second comparison value corresponding to the absolute value.

12 . A method for processing input data including a first component and a second component by a processing circuit, the method comprising:
outputting, by a first processing stage, a maximum value of an absolute value of the first component and an absolute value of the second component, and a minimum value of an absolute value of the first component and an absolute value of the second component; and outputting, by a second processing stage, an output value corresponding to a sum of seven times the maximum value and four times the minimum value in response to the maximum value being smaller than the minimum value times four.

13 . The method to claim 12 , further comprising:
outputting, by the second processing stage, a first output value corresponding to a sum of seven times the maximum value and four times the minimum value, and a second output value corresponding to a difference between seven times th

Assignees

• Stichting Imec Nederland

Inventors

• Young Alex

Classifications

• G06F7/548 Primary

  Trigonometric functions; Co-ordinate transformations · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/0334

  Processing of samples having at least three levels, e.g. soft decisions · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title