Phase domain calculator clock, ALU, memory, register file, sequencer, latches

Patent metadata

Field	Value
Publication number	US-9853649-B2
Application number	US-201615269245-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Sep 15, 2006
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

First claim

What is claimed is:

1. A phase domain calculator comprising:
(a) a processing clock input, a frequency command word input, an integer term input, a fractional term input, a frequency reference input, and a digital local oscillator output;
(b) instruction and data memory having an input coupled to the processing clock input and instruction and data outputs;
(c) sequencer circuitry having an input coupled to the processing clock input, an input coupled to one of the instruction and data outputs, and decoded instruction signal outputs;
(d) a register file having an input coupled to the processing clock input, a ALU out input, and an intermediate value output;
(e) an ALU having inputs coupled to the frequency command word input, the integer term input, the fractional term input, one of the instruction and data outputs, the intermediate value output, and one of the decoded instruction signal outputs, and having an ALU out output;
(f) a first latch having an input coupled to the frequency reference input and coupling the frequency command word input, the integer term input, and the fractional term input to an input of the ALU; and
(g) a second latch having an input coupled to the ALU out output, an input coupled to the frequency reference input, and a digital local oscillator update output.

2. The calculator of claim 1 including an integrated circuit carrying the calculator.

3. The calculator of claim 1 including:
a digitally controlled oscillator having an input coupled with the digital local oscillator update output and an output frequency clock output;
an integer feedback circuit having an input coupled with the output frequency clock output and an output coupled with the integer term input;
a fractional feedback circuit having an input coupled with the output frequency clock output and an output coupled with the fractional term input; and
a programmable fractional-N clock divider having an input coupled with the output frequency clock output and a processing clock output coupled with the processing clock input.

4. The calculator of claim 3 in which the output frequency clock output carries a radio frequency output frequency clock signal.

5. The calculator of claim 3 including a radio having a transmitter coupled to an antennae, the transmitter being coupled to the output frequency clock output.

6. The calculator of claim 1 in which the frequency reference clock input receives a clock signal between about 13 to 52 Megahertz and the processing clock output carries a clock signal between about 200 to 600 Megahertz.

Assignees

• Texas Instruments Inc

Inventors

• Staszewski Roman
• Staszewski Robert B
• Shi Fuqiang

Classifications

• H04B1/04

  Circuits · CPC title

• H03L7/1974

  for fractional frequency division · CPC title

• G06F17/10

  Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• G06F7/605

  Additive or subtractive mixing of two pulse rates into one (beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00) · CPC title