All digital phase locked loop

Patent metadata

Field	Value
Publication number	US-9608641-B2
Application number	US-201615211559-A
Country	US
Kind code	B2
Filing date	Jul 15, 2016
Priority date	Jul 17, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

An all-digital phase-locked loop (AD-PLL) and related methods and computer readable medium are provided. The AD-PLL comprises a reference phase generator for receiving a digital signal and splitting the digital signal into an integer part and a fractional part, an estimator block for estimating a control signal, and a digital-to-time converter for receiving the estimated control signal and a reference clock signal and for deriving a delayed reference clock signal. The AD-PLL also includes a time-to-digital converter for receiving the delayed reference clock signal and a desired clock signal phase, and for deriving a fractional phase error. The estimator block receives the fractional phase error and determines the estimated control signal by correlating the fractional phase error with the fractional part, yielding a correlated signal, multiplying the correlated signal with its absolute value, and integrating the outcome of the multiplying to obtain the estimated control signal.

First claim

The invention claimed is:

1. An all-digital phase-locked loop comprising:
a reference phase generator configured to receive a digital signal and split the received digital signal into an integer part and a fractional part;
an estimator block configured to determine an estimated control signal;
a digital-to-time converter configured to (i) receive the estimated control signal, (ii) receive a reference clock signal, and (iii) derive a delayed reference clock signal based on the reference clock signal and the estimated control signal; and
a time-to-digital converter configured to (i) receive the delayed reference clock signal, (ii) receive a desired clock signal phase, and (iii) derive a fractional phase error based on the delayed reference clock signal and the desired clock signal phase,
wherein the estimator block is further configured to receive the fractional phase error, and wherein determining the estimated control signal comprises:
determining a correlated signal by correlating the fractional phase error with a version of the fractional part having zero mean;
multiplying the correlated signal with an absolute value of the correlated signal; and
integrating the outcome of the multiplication.

2. The all-digital phase-locked loop of claim 1 , wherein the estimator block is further configured to determine the estimated control signal by performing a truncation on the outcome of the multiplication.

3. The all-digital phase-locked loop of claim 2 , wherein the estimator block is further configured to scale the estimated control signal before performing the truncation.

4. The all-digital phase-locked loop of claim 1 , wherein the estimator block is further configured to perform clamping on the estimated control signal.

5. The all-digital phase-locked loop of claim 1 , wherein the multiplication is performed with a power of the absolute value.

6. The all-digital phase-locked loop of claim 1 , further comprising a digital loop filter configured to receive the fractional phase error and an integer phase error, wherein the integer phase error is obtained by computing a difference between the integer part and a variable phase signal.

7. The all-digital phase-locked loop of claim 6 , further comprising a digital clock oscillator coupled to the digital loop filter and configured to output the desired clock signal phase.

8. A method comprising:
receiving, by a reference phase generator, a digital signal;
splitting the received digital signal into an integer part and a fractional part;
determining, by an estimator block, an estimated control signal;
receiving, by a digital-to-time converter, the estimated control signal and a reference clock signal;
deriving, by the digital-to-time converter, a delayed reference clock signal using the reference clock signal and the estimated control signal;
receiving, by a time-to-digital converter, the delayed reference clock signal and a desired clock signal phase;
deriving, by the time-to-digital converter, a fractional phase error;
wherein the estimator block receives the fractional phase error and wherein determining, by the estimator block, the estimated control signal comprises:
determining a correlated signal by correlating the fractional phase error with a version of the fractional part having zero mean;
multiplying the correlated signal with an absolute value of the correlated signal; and
integrating the outcome of the multiplication.

9. The method of claim 8 , wherein determining, by the estimator block, the estimated control signal further comprises performing a truncation on the outcome of the multiplication.

10. The method of claim 9 , wherein the estimator block is further configured to scale the estimated control signal before performing the truncation.

11. The method of claim 8 , wherein determining, by the estimator block, the estimated control signal further comprises performing clamping on the estimated control signal.

12. The method of claim 8 , wherein the multiplication is performed with a power of the absolute value.

13. The method of claim 8 , further comprising:
receiving, by a digital loop filter, the fractional phase error and an integer phase error, wherein the integer phase error is obtained by computing a difference between the integer part and a variable phase signal.

14. The method of claim 13 , further comprising a digital clock oscillator coupled to the digital loop filter and configured to output the desired clock signal phase.

15. A non-transitory, computer readable memory having stored thereon computer instructions, that when executed by one or more processors cause the performance of a set of acts comprising:
receiving a digital signal;
splitting the received digital signal into an integer part and a fractional part;
determining, by an estimator block, an estimated control signal;
receiving, by a digital-to-time converter, the estimated control signal and a reference clock signal;
deriving, by the digital-to-time converter, a delayed reference clock signal using the reference clock signal and the estimated control signal;
receiving, by a time-to-digital converter, the delayed reference clock signal and a desired clock signal phase;
deriving, by the time-to-digital converter, a fractional phase error;
wherein the estimator block receives the fractional phase error and wherein determining, by the estimator block, the estimated control signal comprises:
determining a correlated signal by correlating the fractional phase error with a version of the fractional part having zero mean;
multiplying the correlated signal with an absolute value of the correlated signal; and
integrating the outcome of the multiplication.

16. The non-transitory, computer readable memory of claim 15 , wherein determining, by the estimator block, the estimated control signal further comprises performing a truncation on the outcome of the multiplication.

17. The non-transitory, computer readable memory of claim 16 , wherein the estimator block is further configured to scale the estimated control signal before performing the truncation.

18. The non-transitory, computer readable memory of claim 15 , wherein determining, by the estimator block, the estimated control signal further comprises performing clamping on the estimated control signal.

19. The non-transitory, computer readable memory of claim 15 , wherein the multiplication is performed with a power of the absolute value.

20. The non-transitory, computer readable memory of claim 15 , further comprising:
receiving, by a digital loop filter, the fractional phase error and an integer phase error, wherein the integer phase error is obtained by computing a difference between the integer part and a variable phase signal; and
outputting the desired clock signal phase based on the fractional phase error and integer phase error.

Assignees

• Stichting Imec Nederland

Inventors

• Van Den Heuvel Johan

Classifications

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title