Interconnect reliability structures

Patent metadata

Field	Value
Publication number	US-2017242067-A1
Application number	US-201615048704-A
Country	US
Kind code	A1
Filing date	Feb 19, 2016
Priority date	Feb 19, 2016
Publication date	Aug 24, 2017
Grant date	—

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

First claim

What is claimed:

1 . A structure, comprising:
a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

2 . The structure of claim 1 , wherein the plurality of resistors comprise a first set of resistors having a first polarity and a second set of resistors having a second polarity.

3 . The structure of claim 2 , wherein the first set of resistors and the second set of resistors form a Wheatstone bridge.

4 . The structure of claim 2 , wherein the first set of resistors is configured to sense via depletion caused by electromigration and the second set of resistors is configured to sense line depletion caused by electromigration.

5 . The structure of claim 4 , wherein:
the plurality of resistors each comprise a dual damascene structure and an interconnect via structure in direct electrical connection with a wiring layer of the dual damascene structure; a liner material between the wiring layer of the dual damascene structure and the interconnect via structure; and a junction of the wiring layer and a via interconnect structure of the dual damascene structure is devoid of the liner material.

6 . The structure of claim 5 , wherein the second set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from the interconnect via structure into the dual damascene structure.

7 . The structure of claim 5 , wherein the first set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from the dual damascene structure into the interconnect via structure.

8 . The structure of claim 5 , wherein the plurality of resistors are each comprised of via chain structures comprising a single via interconnect on one side of the wiring layer and a plurality of via interconnects on another side of the wiring layer, each of which are in direct electrical contact with an upper wiring layer.

9 . The structure of claim 8 , wherein the plurality of via interconnects on the other side of the wiring layer has a lower resistance than the single via interconnect.

10 . The structure of claim 1 , wherein the plurality of resistors are connected to a wiring structure which has a line width greater than a line width of each of the resistors.

11 . A structure, comprising:
a first set of resistors having a first polarity; a second set of resistors having a second polarity; and a voltmeter configured to sense a relative difference in resistance between the first set of resistors and the second sets of resistors.

12 . The structure of claim 11 , wherein the first set of resistors and the second set of resistors form a Wheatstone bridge.

13 . The structure of claim 12 , wherein the first set of resistors comprise a via depletion electromigration structure and the second set of resistors comprise a line depletion electromigration structure.

14 . The structure of claim 13 , wherein the second set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from an interconnect via structure into a dual damascene structure.

15 . The structure of claim 13 , wherein the first set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from a dual damascene structure into an interconnect via structure.

16 . The structure of claim 11 , wherein the plurality of resistors are each comprised of via chain structures comprising a single via interconnect on one side of the wiring layer and a plurality of via interconnects on another side of the wiring layer, each of which are in direct electrical contact with an upper wiring layer.

17 . The structure of claim 16 , wherein plurality of via interconnects on the other side of the wiring layer has a lower resistance than the single via interconnect.

18 . The structure of claim 11 , wherein the plurality of resistors are connected to a wiring structure which has a line width greater than a line width of each of the resistors.

19 . A method, comprising:
continuously monitoring a voltage V WB during in-line current ramp; and determining a statistically significant direction of V WB shift in real time during the current ramp.

20 . The method of claim 19 , wherein:
no statistically significant shift direction in V WB is indicative of no electromigration defects being found; and an increase or decrease of shift direction in V WB will be indicative of via defects or line defects.

Assignees

• Globalfoundries Inc

Inventors

• Wang Ping-Chuan
• Kim Andrew T
• Filippi Ronald G

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G01R31/2858 Primary

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title

• H01L23/5226

  Electricity · mapped topic