Bridge interconnection with layered interconnect structures

Patent metadata

Field	Value
Publication number	US-2017207168-A1
Application number	US-201715478858-A
Country	US
Kind code	A1
Filing date	Apr 4, 2017
Priority date	May 28, 2013
Publication date	Jul 20, 2017
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a substrate; a bridge embedded in the substrate, the bridge being configured to route electrical signals between a first die and a second die, wherein the substrate is a first substrate and the bridge includes a bridge substrate that comprises a semiconductor material including silicon (Si), and wherein the first substrate comprises an epoxy-based dielectric material; and an interconnect structure electrically coupled with the bridge, the interconnect structure including:
a via structure including a first conductive material, the via structure being disposed to route the electrical signals through at least a portion of the substrate,
a barrier layer including a second conductive material disposed on the via structure, and
a solderable material including a third conductive material disposed on the barrier layer, wherein the first conductive material, the second conductive material and the third conductive material have different chemical composition.

2 . The apparatus of claim 1 , wherein:
the bridge includes a pad; and the first conductive material is in direct contact with the pad.

3 . The apparatus of claim 1 , wherein the via structure protrudes beyond a surface of an outermost build-up layer of the substrate.

4 . The apparatus of claim 1 , wherein the barrier layer covers a surface of the via structure to inhibit diffusion of the first conductive material.

5 . The apparatus of claim 1 , wherein the first die includes a processor and the second die includes a memory die or another processor.

6 . The apparatus of claim 1 , wherein the electrical signals are input/output (I/O) signals.

Assignees

• Intel Corp

Inventors

• Liu Yueli
• Zhang Qinglei
• Schuckman Amanda E
• Zhang Rui

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title