Engineering change order (eco) cell, layout thereof and integrated circuit including the eco cell

Patent metadata

Field	Value
Publication number	US-2017116366-A1
Application number	US-201615236654-A
Country	US
Kind code	A1
Filing date	Aug 15, 2016
Priority date	Oct 26, 2015
Publication date	Apr 27, 2017
Grant date	—

Abstract

An engineering change order (ECO) base cell and an integrated circuit (IC) including the ECO base cell are provided. The IC includes a plurality of standard cells and at least one engineering change order (ECO) base cell. The ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates.

First claim

1 . An integrated circuit (IC) comprising:
a plurality of standard cells; and at least one engineering change order (ECO) base cell, wherein the ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates.

2 . The IC of claim 1 , wherein the ECO base cell has a layout obtained by removing a metal layer and/or a via connected to the metal layer from the layout of the functional cell corresponding to the first circuit.

3 . The IC of claim 1 , wherein the layout of the ECO base cell comprises at least three gate lines that are parallel to one another.

4 . The IC of claim 1 , further comprising an ECO functional cell having a layout obtained by adding a pattern of a metal layer and a via connected to the pattern to the layout of the ECO base cell.

5 . The IC of claim 4 , wherein the ECO functional cell corresponds to a second circuit including at least one of the plurality of logic gates.

6 . The IC of claim 5 , wherein the second circuit is identical with the first circuit.

7 . The IC of claim 5 , wherein the second circuit comprises at least two logic gates, wherein the second circuit comprises first and second subcircuits, each of which comprises at least one of the at least two logic gates, and
the first and second subcircuits are insulated from each other in the ECO functional cell.

8 . The IC of claim 1 , wherein the ECO base cell is a filler cell or a decoupling capacitor cell placed in a spare region of a layout of the IC.

9 . The IC of claim 1 , wherein the functional cell is a standard cell.

10 . An engineering change order (ECO) base cell having a layout obtained by removing a metal layer and/or a via connected to the metal layer from a layout of a functional cell corresponding to a first circuit including a plurality of logic gates.

11 . The ECO base cell of claim 10 , wherein the layout of the ECO base cell comprises at least three gate lines that are parallel to each other.

12 . The ECO base cell of claim 10 , wherein the functional cell is a standard cell.

13 . The ECO base cell of claim 10 , wherein the first circuit is a sequential circuit or a combinational circuit.

14 . The ECO base cell of claim 13 , wherein the first circuit is a flip-flop or a latch.

15 . The ECO base cell of claim 13 , wherein the first circuit is a multiplexer, an adder, or an XOR gate.

16 . An integrated circuit device, comprising:
a plurality of interconnected standard logic cells distributed within a standard cell region of a substrate; and at least a first engineering change order (ECO) base cell within a spare region of the substrate extending adjacent the standard cell region, said first ECO base cell having an in-substrate layout corresponding to an in-substrate layout of a functional logic cell and an above-substrate layout that is incomplete relative to an above-substrate layout of the functional logic cell.

17 . The device of claim 16 , wherein the above-substrate layout of said first ECO base cell is missing at least one electrically conductive via and/or at least one metal interconnect relative to the above-substrate layout of the functional logic cell.

18 . The device of claim 17 , wherein said first ECO base cell is configured to be functionally and layout equivalent to the functional logic cell upon addition of the missing at least one electrically conductive via and/or the at least one metal interconnect to said first ECO base cell.

19 . The device of claim 16 , wherein said first ECO base cell is configured as a decoupling capacitor.

20 . The device of claim 17 , wherein the functional logic cell is equivalent to a standard logic cell in said plurality of interconnected standard logic cells.

21 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Jae-Woo
• Lee Dal-Hee

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/23

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G06F17/5077 Primary

  Physics · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H10D84/90

  Masterslice integrated circuits · CPC title