Modified standard cells to address fast paths

Patent metadata

Field	Value
Publication number	US-9280630-B1
Application number	US-201414535701-A
Country	US
Kind code	B1
Filing date	Nov 7, 2014
Priority date	Nov 7, 2014
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

Circuitry including a logic circuitry portion and a delay circuitry portion, with the circuitry having the following features: (i) the logic circuitry is designed to receive a set of input signals including a first input signal and a second input signal; and (ii) the delay circuitry portion includes a transistor connected so that the first input signal gates the second input signal. In some embodiments, the first and second input signals are chosen because it is expected that the second input signal will arrive at the circuitry before the first input signal so that the gating of the second signal by the first signal will cause the logic circuitry portion to receive the first and second signals at substantially the same time. Also, circuitry where a first output signal from a logic circuitry portion is gated by a second output signal.

First claim

What is claimed is:

1. Circuitry comprising:
a logic circuitry portion; and
a delay circuitry portion including a first transistor;
wherein:
the logic circuitry portion is structured and/or electrically connected to: (i) receive a set of input signals including at least a first input signal and a second input signal; and (ii) perform logic functionality on the set of input signals to generate a set of output signal(s); and
the first transistor is structured and/or electrically connected to gate the first input signal with the second input signal so that the first input signal is not received by the logic circuitry portion until the second input signal has arrived at the first transistor.

2. The circuitry of claim 1 wherein the logic circuitry portion and delay circuitry portion are integrated into an integrated circuit.

3. The circuitry of claim 2 wherein the integrated circuit is designed so that the first input signal arrives at the first transistor before the second input signal arrives at the first transistor.

4. The circuitry of claim 3 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR and/or complex gates using sub-combinations of the foregoing types of logic functionality.

5. The circuitry of claim 1 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR and/or complex gates using sub-combinations of the foregoing types of logic functionality.

6. Circuitry comprising:
a logic circuitry portion; and
a delay circuitry portion including a first transistor;
wherein:
the logic circuitry portion is structured and/or electrically connected to: (i) receive a set of input signal(s); and (ii) perform logic functionality on the set of input signals to generate a set of output signal(s) including at least a first output signal and a second output signal; and
the first transistor is structured and/or electrically connected to gate the first output signal with the second output signal so that the first output signal is not output by the logic circuitry portion until the second output signal has arrived at the first transistor.

7. The circuitry of claim 6 wherein the logic circuitry portion and delay circuitry portion are integrated into an integrated circuit.

8. The circuitry of claim 7 wherein the integrated circuit is designed so that the first output signal arrives at the first transistor before the second output signal arrives at the first transistor.

9. The circuitry of claim 8 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR and/or complex gates using sub-combinations of the foregoing types of logic functionality.

10. The circuitry of claim 6 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR and/or complex gates using sub-combinations of the foregoing types of logic functionality.

11. A method of designing an integrated circuit, the method comprising:
defining a set of standard cell(s) including code based representations of a logic circuitry portion, and a delay circuitry portion including a first transistor; and
applying the set of standard cell(s) into an integrated circuit design so that:
the logic circuitry portion is structured and/or electrically connected to: (i) receive a set of input signals including at least a first input signal and a second input signal; and (ii) perform logic functionality on the set of input signals to generate a set of output signal(s), and
the first transistor is structured and/or electrically connected to gate the first input signal with the second input signal so that the first input signal is not received by the logic circuitry portion until the second input signal has arrived at the first transistor.

12. The method of claim 11 wherein the application of the set of standard cell(s) is performed so that the first input signal arrives at the first transistor before the second input signal arrives at the first transistor.

13. The method of claim 11 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR and/or complex gates using sub-combinations of the foregoing types of logic functionality.

14. The method of claim 11 wherein:
the definition of the set of standard cell(s) is performed so that the delay circuitry and the logic circuitry are both included in a single standard cell.

Assignees

• IBM

Inventors

• Lewis Daniel
• Rao Rahul M
• Subramanya Adarsh

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/35 Primary

  Delay-insensitive circuit design, e.g. asynchronous or self-timed · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/096 Primary

  Synchronous circuits, i.e. using clock signals {(H03K19/01728, H03K19/01855 take precedence)} · CPC title

• G06F17/5059 Primary

  Physics · mapped topic