Standard cell layout, semiconductor device having engineering change order (ECO) cells and method

Patent metadata

Field	Value
Publication number	US-9831230-B2
Application number	US-201313965648-A
Country	US
Kind code	B2
Filing date	Aug 13, 2013
Priority date	Aug 13, 2013
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

First claim

What is claimed is:

1. A layout of a standard cell, the layout when executed by a computer, fabricating a semiconductor device including the layout, the layout comprising:
a first conductive pattern;
a second conductive pattern;
a plurality of active area patterns isolated from each other and arranged in a first row and a second row between the first and second conductive patterns,
the first row adjacent the first conductive pattern and comprising a first active area pattern and a second active area pattern among the plurality of active area patterns, and
the second row adjacent the second conductive pattern and comprising a third active area pattern and a fourth active area pattern among the plurality of active area patterns;

a first central conductive pattern arranged between the first and second active area patterns, the first central conductive pattern overlapping the first conductive pattern; and
for each of the plurality of active area patterns, two additional conductive patterns overlapping the active area pattern, wherein the additional conductive patterns are discontinuous between adjacent active area patterns of the plurality of active area patterns, the additional conductive patterns and the first central conductive pattern belong to a first conductive layer in the layout, and the additional conductive patterns do not overlap the first and second conductive patterns.

2. The layout of claim 1 , further comprising:
a second central conductive pattern arranged between the third and fourth active area patterns, the second central conductive pattern overlapping the second conductive pattern.

3. The layout of claim 2 , wherein the second central conductive pattern is isolated from the first central conductive pattern.

4. The layout of claim 2 , wherein the first and second central conductive patterns are arranged along a symmetric axis of the standard cell.

5. The layout of claim 1 , further comprising:
for each of the plurality of active area patterns, at least one conductive gate pattern overlapping the active area pattern.

6. The layout of claim 5 , wherein
the at least one conductive gate pattern overlapping the first active area pattern and the at least one conductive gate pattern overlapping the third active area pattern are continuous with each other and define a first common conductive gate pattern overlapping both the first and third active area patterns, and
the at least one conductive gate pattern overlapping the second active area pattern and the at least one conductive gate pattern overlapping the fourth active area pattern are continuous with each other and define a second common conductive gate pattern overlapping both the second and fourth active area patterns.

7. The layout of claim 5 , wherein the additional conductive patterns are arranged on opposite sides of the corresponding at least one conductive gate pattern.

8. The layout of claim 1 , wherein the first and second conductive patterns belong to a second conductive layer above the first conductive layer;
the layout further comprising:
a via layer disposed between the first and second conductive layers, the via layer comprising at least one via electrically connecting the first central conductive pattern with the first conductive pattern.

9. The layout of claim 8 , wherein the via layer further comprises
a plurality of vias each electrically connected with one of the additional conductive patterns.

10. The layout of claim 1 , further comprising:
for each of the plurality of active area patterns, more than one conductive gate patterns overlapping the active area pattern.

11. A layout of a standard cell, the layout when executed by a computer, fabricating a semiconductor device including the layout, the layout comprising:
a first conductive pattern;
a second conductive pattern;
a plurality of active area patterns isolated from each other and arranged between the first and second conductive patterns;
a first central conductive pattern overlapping the first conductive pattern, wherein a length of the first central conductive pattern extends along a reference axis; and
a second central conductive pattern aligned with the first central conductive pattern along the reference axis and overlapping the second conductive pattern, wherein the second central conductive pattern is discontinuous with the first central conductive pattern, and the plurality of active area patterns is arranged symmetrically about the reference axis;
a polysilicon pattern overlapping at least two active area patterns of the plurality of active area patterns;
two additional conductive patterns overlapping the at least two active area patterns and arranged on opposite sides of the polysilicon pattern, wherein
the two additional conductive patterns and the first and second central conductive patterns corresponding to forming conductive structures of a first conductive layer, and
the first and second conductive patterns corresponding to forming conductive structures of a second conductive layer above the first metal layer; and

via layout patterns corresponding to a via layer disposed between the first and second conductive layers, the via layer comprising at least one of
a first via electrically connecting a conductive structure corresponding to the first central conductive pattern with a conductive structure corresponding to the first conductive pattern,
a second via electrically connecting a conductive structure corresponding to the second conductive metal pattern with a conductive structure corresponding to the second conductive pattern, and
a plurality of vias each electrically connected with a conductive structure corresponding to one of the two additional conductive patterns.

12. The layout of claim 11 , wherein the second central conductive pattern is electrically connected to the second conductive pattern by a via.

13. The layout of claim 11 , wherein at least one of the cells is in an unprogrammed state in which the conductive structure corresponding to the polysilicon patterns and the conductive structure corresponding to the additional conductive patterns are electrically isolated from the conductive structures corresponding to the first and second metal patterns and first and second central metal patterns.

14. The layout of claim 11 , wherein at least one of the cells is in a programmed state in which the conductive structure corresponding to the polysilicon patterns is electrically connected with at least one of the first and second conductive patterns and first and second central conductive patterns, through one or more vias in the via layer and one or more connection conductive patterns in the second conductive layer.

15. A layout of a standard cell, the layout when executed by a computer, fabricating a semiconductor device including the layout, the layout comprising:
a first conductive pattern;
a second conductive pattern, wherein the first conductive pattern and the second conductive pattern belong to a second conductive layer above a first conductive layer;
a plurality of active area patterns isolated from each other and arranged between the first and second conductive patterns;
a first central conductive pattern arranged between a first active area pattern and a second active area pattern of the plurality of active area patterns, the first central conductive pattern overlapping the first conductive pattern;
a second central conductive pattern arranged between a third active area pattern and a fourth active area patterns of the plurality of active area patterns, the second central conductive pattern overlapping the sec

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tien Li-Chun
• Chou Ya-Chi
• Zhuang hui-zhong
• Chen Chun-Fu
• Chiang Ting-Wei
• Tseng Hsiang Jen

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L27/11807

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L2027/11875

  Electricity · mapped topic

• G06F17/5068

  Physics · mapped topic