Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-2017077007-A1
Application number	US-201615361487-A
Country	US
Kind code	A1
Filing date	Nov 27, 2016
Priority date	Jun 8, 2014
Publication date	Mar 16, 2017
Grant date	—

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die; and an encapsulant material, wherein the encapsulant material is disposed on and covers at least a portion of the first and second sidewalls of the die.

2 . The semiconductor package of claim 1 , wherein the first and second sidewalls include vertical sidewall profile and the encapsulant material fully covers the first and second sidewalls of the die.

3 . The semiconductor package of claim 2 , wherein the encapsulant material fully covers the first and second sidewalls and the first and second major surfaces of the die, wherein the encapsulant material includes a single encapsulant layer which extends continuously over the sidewalls and the major surfaces of the die.

4 . The semiconductor package of claim 2 , wherein the encapsulant material includes a single encapsulant layer that fully covers the first and second sidewalls and the first major surface of the die, wherein the single encapsulant layer includes a thickness which is less than a height of the external electrical contacts,

5 . The semiconductor package of claim 4 , wherein the single encapsulant layer comprises non-uniform thickness across the first major surface of the die.

6 . The semiconductor package of claim 2 , wherein the encapsulant material includes a single encapsulant layer that fully covers the first and second sidewalls of the die, wherein the single encapsulant layer does not contact the external electrical contacts of the die.

7 . The semiconductor package of claim 2 comprising a backside protective layer disposed over the second major surface of the die, wherein the encapsulant material includes a single encapsulant layer that fully covers the first and second sidewalls of the die and the backside protective layer fully covers the second major surface of the die.

8 . The semiconductor package of claim 7 wherein the single encapsulant layer extends along the first and second sidewalls to cover side surfaces of the backside protective layer.

9 . The semiconductor package of claim 7 wherein the single encapsulant layer includes substantially arc shape profiles disposed over the first and the second sidewalls of the die.

10 . The semiconductor package of claim 2 wherein the encapsulant material comprises vertical portions and first and second lateral extended portions, wherein
the vertical portions fully cover the first and second sidewalls of the die, and
the first lateral extended portions extend over peripheral portions of the first major surface of the die and the second lateral extended portions extend away from the die, the second lateral extended portions include a top surface which is substantially coplanar with the second major surface of the die.

11 . The semiconductor package of claim 1 wherein the encapsulant material comprises a first encapsulant layer that covers the first major surface of the die and a second encapsulant layer disposed over the first encapsulant layer, wherein the first and second encapsulant layers are separate and distinct layers, wherein a total thickness of the first and second encapsulant layers is less than a height of the external electrical contacts.

12 . The semiconductor package of claim 1 wherein each of the first and second sidewalls of the die include a step profile and the encapsulant material covers at least a portion of the first and second sidewalls of the die.

13 . The semiconductor package of claim 12 wherein the encapsulant material comprises a first encapsulant layer that covers the first major surface of the die and a second encapsulant layer that covers the first encapsulant layer and a portion of the first and second sidewalls of the die and.

14 . A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die; and an encapsulant material, wherein the encapsulant material covers at least a portion of the first and second sidewalls of the die, wherein the encapsulant material is in direct contact with the first and second sidewalls without contacting the external electrical contacts of the die.

15 . The semiconductor package of claim 14 , wherein the encapsulant material includes a single encapsulant layer that completely covers the first and second sidewalls and the second major surface of the die.

16 . The semiconductor package of claim 14 , wherein portions of the encapsulant material extending along the first and second sidewalls of the die comprises a non-uniform thickness.

17 . The semiconductor package of claim 14 comprising a backside protective layer, wherein the backside protective layer completely covers the second major surface of the die, the backside protective layer includes a material different from the encapsulant material.

18 . A semiconductor package comprising:
a semiconductor die, wherein the die comprises first and second major surfaces and first and second sidewalls, and a plurality of external electrical contacts disposed on the first major surface of the die; and an encapsulant material, wherein the encapsulant material directly contacts the first and second sidewalls of the die, wherein the first and second sidewalls include a step profile.

19 . The semiconductor package of claim 18 comprising:
a first encapsulant layer covering the first major surface of the die; and
a second encapsulant layer covering the first encapsulant layer and a portion of the first and second sidewalls of the die, wherein the first and second encapsulant layers are separate and distinct layers.

20 . The semiconductor package of claim 18 , wherein the encapsulant material covers at least a portion of the first and second sidewalls of the die without extending over the second major surface of the die.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Dimaano Antonio Jr Bambalan
• Huang Rui
• Tan Hua Hong
• Le Kriangsak Sae
• Ho Beng Yeung
• De Vera Nelson Agbisit
• Robles Roel Adeva
• Micla Wedanni Linsangan

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W46/301

  for alignment · CPC title