Edge trim processes and resultant structures

Patent metadata

Field	Value
Publication number	US-2016343564-A1
Application number	US-201514718747-A
Country	US
Kind code	A1
Filing date	May 21, 2015
Priority date	May 21, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.

First claim

What is claimed:

1 . A method, comprising:
trimming an edge of a wafer at an angle to form a sloped sidewall; attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer; and thinning the wafer while it is attached to the wafer.

2 . The method of claim 1 , wherein the trimming of the edge forms a bevel about the wafer.

3 . The method of claim 1 , wherein the sloped sidewall is formed from a top surface to a bottom surface of the wafer.

4 . The method of claim 3 , wherein the trimming results in the bottom surface having a diameter that is less than a top surface of the wafer.

5 . The method of claim 4 , wherein the diameter of the bottom surface is 1-10 mm less than the diameter of the upper surface.

6 . The method of claim 4 , wherein the sloped sidewall is at an angle from about 10° to about 80°.

7 . The method of claim 3 , wherein the sloped sidewall is formed from a straight sidewall to a bottom surface of the wafer.

8 . The method of claim 7 , wherein the thinning removes the straight sidewall and portions of the sloped sidewall.

9 . The method of claim 3 , wherein the sloped sidewall is formed from a top surface of the wafer to a pedestal that is formed by straight edge cut at a bottom portion of the wafer.

10 . The method of claim 9 , wherein the pedestal is formed to a height of about 15 to 50 μm.

11 . The method of claim 1 , wherein the thinning of the wafer is a grinding starting from a larger diameter surface to a smaller diameter surface, closest to the carrier wafer.

12 . A method comprising:
forming a beveled edge with a top surface having a diameter smaller than a diameter of a bottom surface; bonding the bottom surface of the wafer to a carrier wafer; and grinding the wafer to a predetermined thickness while it remains bonded to the carrier wafer.

13 . The method of claim 12 , wherein the beveled edge extends from the top surface to the bottom surface of the wafer.

14 . The method of claim 12 , wherein the beveled edge is at an angle from about 10° to about 80°.

15 . The method of claim 12 , wherein the beveled edge is formed from a straight sidewall at an upper portion of the wafer to the bottom surface of the wafer.

16 . The method of claim 15 , wherein the thinning removes the straight sidewall and portions of the beveled edge.

17 . The method of claim 12 , wherein the beveled edge is formed from the top surface of the wafer to a pedestal that is formed by straight edge cut at a bottom portion of the wafer.

18 . The method of claim 17 , wherein the pedestal is attached to the carrier wafer.

19 . The method of claim 12 , wherein the grinding starts from a larger diameter surface to a smaller diameter surface of the wafer.

20 . A structure comprising:
a non-edge trimmed carrier wafer; and a wafer with a beveled edge about a diameter bonded to the non-edge trimmed carrier wafer, wherein a surface which is bonded to the non-edge trimmed carrier wafer is smaller than an original diameter of the wafer, in a non-edge trimmed state.

Assignees

• IBM

Inventors

• Indyk Richard F
• Priyadarshini Deepika
• Skordas Spyridon
• Sprogis Edmund J
• Stamper Anthony K
• Winstel Kevin R

Classifications

• H10P90/128

  by edge treatment, e.g. chamfering · CPC title

• H10P90/123

  by grinding or lapping · CPC title

• H10P90/18 Primary

  by shaping · CPC title

• H01L21/02035 Primary

  Electricity · mapped topic

• H01L21/02021

  Electricity · mapped topic