Stacked semiconductor device structure and method

Patent metadata

Field	Value
Publication number	US-9711434-B2
Application number	US-201615219000-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Sep 17, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A stacked semiconductor device structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed surface portion bounded by opposing sidewall portions extending outward to define a recessed region. A conductive layer is disposed along at least the recessed surface portion. The second semiconductor device is disposed within the recessed region and is electrically connected to the conductive layer. In one embodiment, the stacked semiconductor device is connected to a conductive lead frame and is at least partially encapsulated by a package body.

First claim

We claim:

1. A stacked semiconductor device structure comprising:
a first semiconductor device comprising:
a first singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface, the second major surface comprising a recessed surface portion bounded by opposing sidewall portions extending outward from the recessed surface portion in cross-sectional view to define a recessed region, the sidewall portions having outer surfaces defining peripheral edge segments of the first singulated region of semiconductor material, the sidewall portions further comprising inner surfaces opposite to the outer surfaces;
a first active device region disposed adjacent to the first major surface; and
a first conductive layer disposed adjoining the recessed surface portion; and

a second semiconductor device comprising:
a second singulated region of semiconductor material having a third major surface and a fourth major surface opposite to the third major surface; and
a second active device region disposed adjacent to the third major surface, wherein:
a first portion of the second semiconductor device is electrically coupled to the first conductive layer within the recessed region, and
at least a portion of the second semiconductor device is disposed within the recessed region.

2. The structure of claim 1 further comprising:
a conductive lead frame comprising a plurality of conductive lead structures; and
a package body encapsulating at least portions of the conductive lead frame, the first semiconductor device, and the second semiconductor device, wherein:
the sidewall portions are electrically coupled to a first conductive lead structure and a second conductive lead structure respectively;
the fourth major surface is electrically coupled to a third conductive lead structure;
a portion of the first semiconductor device is electrically coupled to a fourth conductive lead structure; and
portions of the first conductive lead structure, the second conductive lead structure, the third conductive lead structure, and the fourth conductive lead structure are exposed to an outside of the package body.

3. The structure of claim 2 , wherein:
another portion of the first semiconductor device is electrically coupled to a fifth conductive lead structure; and
a second portion of the second semiconductor device is electrically coupled to a sixth conductive lead structure.

4. The structure of claim 3 , wherein:
a third portion of the second semiconductor device is electrically coupled to a seventh conductive lead structure; and
portions of the fifth conductive lead structure, the sixth conductive lead structure, and the seventh conductive lead structure are exposed to the outside of the package body.

5. The structure of claim 4 , wherein:
the third portion of the second semiconductor device comprises a gate electrode region; and
the second portion and the first portion of the second semiconductor device comprise a source electrode.

6. The structure of claim 3 , wherein the second portion of the second semiconductor device is electrically coupled to the sixth conductive lead structure using a through-semiconductor via.

7. The structure of claim 2 further comprising a third semiconductor device electrically coupled to a first control electrode of the first semiconductor device and electrically coupled to a second control electrode of the second semiconductor device.

8. The structure of claim 7 , wherein:
the portion of the first semiconductor device is electrically coupled to the fourth conductive lead structure with a conductive clip;
the third semiconductor device is attached to the conductive clip; and
the third semiconductor device is electrically isolated from the conductive clip.

9. The structure of claim 1 , wherein the first conductive layer is disposed along the inner surfaces of the sidewall portions and along tip portions of the sidewall portions, which are distal to the recessed surface portion.

10. The structure of claim 1 , wherein:
the first semiconductor device and the second semiconductor device comprise MOSFETs;
the second semiconductor device is bounded on a first pair of opposing sides by the sidewall portions; and
a second pair of opposing sides of the second semiconductor device extend laterally away from edges of the first semiconductor device.

11. A method of manufacturing a stacked semiconductor device comprising:
providing a first semiconductor device comprising:
a first singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface, the second major surface comprising a recessed surface portion bounded by a first sidewall portion extending outward from the recessed surface portion in cross-sectional view to define a recessed region, the first sidewall portion having an outer surface defining a peripheral edge segment of the first singulated region of semiconductor material, the first sidewall portion further comprising an inner surface opposite to the outer surface;
a first active device region disposed adjacent to the first major surface; and
a first conductive layer disposed adjoining at least the recessed surface portion;

providing a second semiconductor device comprising:
a second singulated region of semiconductor material having a third major surface and a fourth major surface opposite to the third major surface; and
a second active device region disposed adjacent to the third major surface; and

electrically coupling a first portion of the second semiconductor device to the first conductive layer within the recessed surface portion.

12. The method of claim 11 wherein:
providing the first semiconductor device comprises providing a second sidewall portion disposed opposite to the first sidewall portion; and
the method further comprises:
providing a conductive substrate comprising a plurality of conductive lead structures;
electrically coupling the first sidewall portion to a first conductive lead structure and the second sidewall portion to a second conductive lead structure;
electrically coupling the fourth major surface to a third conductive lead structure;
electrically coupling a portion of the first semiconductor device to a fourth conductive lead structure; and
forming a package body encapsulating at least portions of the conductive substrate, the first semiconductor device, and the second semiconductor device, wherein portions of the first conductive lead structure, the second conductive lead structure, the third conductive lead structure, and the fourth conductive lead structure are exposed to an outside of the package body.

13. The method of claim 12 further comprising:
electrically coupling another portion of the first semiconductor device to a fifth conductive lead structure;
electrically coupling a second portion of the second semiconductor device to a sixth conductive lead structure; and
electrically coupling a third portion of the second semiconductor device to a seventh conductive lead structure, wherein portions of the fifth conductive lead structure, the sixth conductive lead structure, and the seventh conductive lead structure are exposed to the outside of the package body.

14. The method of claim 13 , wherein the step of electrically coupling the second portion of the second semiconductor device comprises electrically coupling with a through-substrate via.

15. The method of claim 12 further comprising:
providing a third semiconductor device; and
electrically coupling the third semicondu

Assignees

• Semiconductor Components Ind Llc

Inventors

• Seddon Michael J
• Carney Francis J

Classifications

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title