Reduction of defect induced leakage in iii-v semiconductor devices

US2016336408A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016336408-A1
Application numberUS-201615135148-A
CountryUS
Kind codeA1
Filing dateApr 21, 2016
Priority dateMay 11, 2015
Publication dateNov 17, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 8 cm −2 . An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device, comprising: a p-doped layer formed on a substrate having a dislocation density; and an n-type layer formed on or in the p-doped layer, the n-type layer including a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer. 2 . The semiconductor device as recited in claim 1 , further comprising a buffer layer disposed between the p-doped layer and the substrate, wherein the buffer layer includes at least one layer configured to lattice match adjacent layers. 3 . The semiconductor device as recited in claim 2 , wherein the buffer layer includes a plurality of layers configured to lattice match adjacent layers. 4 . The semiconductor device as recited in claim 2 , wherein the buffer layer includes at least one of Ge, a III-V material, GaAs, InP, or combination thereof. 5 . The semiconductor device as recited in claim 1 , wherein the material for the n-type layer includes a II-VI material. 6 . The semiconductor device as recited in claim 1 , wherein the n-type layer includes at least one of a doped ZnO or an ITO. 7 . The semiconductor device as recited in claim 1 , wherein the n-type layer includes a carrier concentration of between about 1×10 21 cm −3 to about 5×10 21 cm −3 . 8 . The semiconductor device as recited in claim 1 , wherein the n-type layer includes an amorphous phase. 9 . The semiconductor device as recited in claim 1 , wherein the substrate includes silicon and the p-doped layer includes a III-V material. 10 . The semiconductor device as recited in claim 1 , wherein the n-type layer forms source and drain regions for a field effect transistor. 11 . The semiconductor device as recited in claim 1 , wherein the n-type layer forms a diode junction. 12 . The semiconductor device as recited in claim 1 , wherein the electronic device includes an on/off ratio of greater than 1×10 3 . 13 . The semiconductor device as recited in claim 1 , wherein the reduced leakage current is reduced by at least two orders of magnitude. 14 . The semiconductor device as recited in claim 1 , wherein the dislocation density exceeds 10 8 cm −2 . 15 . A semiconductor device, comprising: a Si semiconductor substrate; a buffer formed on the substrate; an InGaAs p-doped layer formed on the buffer; and a ZnO n-type layer formed on or in the p-doped layer, the n-type layer configured to tolerate dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer. 16 . The semiconductor device as recited in claim 15 , wherein the buffer layer includes a plurality of layers configured to lattice match adjacent layers. 17 . The semiconductor device as recited in claim 15 , wherein the n-type layer includes an amorphous phase. 18 . The semiconductor device as recited in claim 15 , wherein the n-type layer forms one of source and drain regions for a field effect transistor or a diode junction. 19 . The semiconductor device as recited in claim 15 , wherein the leakage current is reduced by at least two orders of magnitude. 20 . The semiconductor device as recited in claim 15 , wherein the electronic device includes an on/off ratio of greater than 1×10 3 .

Assignees

Inventors

Classifications

  • further characterised by the dopants · CPC title

  • Source or drain regions of field-effect devices · CPC title

  • being Group II-VI materials, e.g. ZnO · CPC title

  • being Group III-V materials, e.g. GaAs · CPC title

  • PN diodes having the PN junctions in mesas · CPC title

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What does patent US2016336408A1 cover?
A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 8 cm −2 . An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10D62/82. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 17 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).