Reduction of defect induced leakage in III-V semiconductor devices

Patent metadata

Field	Value
Publication number	US-9401397-B1
Application number	US-201514709044-A
Country	US
Kind code	B1
Filing date	May 11, 2015
Priority date	May 11, 2015
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 8 cm −2 . An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a p-doped layer formed on the substrate having a dislocation density exceeding 10 8 cm −2 ; and
an n-type layer formed on or in the p-doped layer, the n-type layer including a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

2. The semiconductor device as recited in claim 1 , wherein the n-type layer includes doped ZnO.

3. The semiconductor device as recited in claim 2 , wherein the n-type layer includes a carrier concentration of between about 1×10 21 cm −3 to about 5×10 21 cm −3 .

4. The semiconductor device as recited in claim 2 , wherein the n-type layer includes an amorphous phase.

5. The semiconductor device as recited in claim 1 , wherein the substrate includes silicon and the p-doped layer includes InGaAs.

6. The semiconductor device as recited in claim 1 , wherein the n-type layer Rums source and drain regions for a field effect transistor.

7. The semiconductor device as recited in claim 1 , wherein the n-type layer forms a diode junction.

8. The semiconductor device as recited in claim 1 , wherein the electronic device includes an on/off ratio of greater than 1×10 3 .

9. The semiconductor device as recited in claim 1 , wherein the reduced leakage current is reduced by at least two orders of magnitude.

10. A semiconductor device, comprising:
a Si semiconductor substrate;
a buffer formed on the substrate;
an InGaAs p-doped layer formed on the buffer; and
a ZnO n-type layer formed on or in the p-doped layer, the n-type layer configured to tolerate dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer, wherein the leakage current is reduced by at least two orders of magnitude.

11. The semiconductor device as recited in claim 10 , wherein the buffer layer includes a plurality of layers configured to lattice match adjacent layers.

12. The semiconductor device as recited in claim 10 , wherein the n-type layer includes a carrier concentration of between about 1×10 21 cm −3 to about 5×10 21 cm −3 .

13. The semiconductor device as recited in claim 10 , wherein the n-type layer includes an amorphous phase.

14. The semiconductor device as recited in claim 10 , wherein the n-type layer forms one of source and drain regions for a field effect transistor or a diode junction.

15. The semiconductor device as recited in claim 10 , wherein the electronic device includes an on/off ratio of greater than 1×10 3 .

16. A semiconductor device, comprising:
a Si semiconductor substrate;
a buffer formed on the substrate;
an InGaAs p-doped layer formed on the buffer; and
a ZnO n-type layer formed on or in the p-doped layer, the n-type layer configured to tolerate dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer, wherein the n-type layer includes an amorphous phase.

17. The semiconductor device as recited in claim 16 , wherein the buffer layer includes a plurality of layers configured to lattice match adjacent layers.

18. The semiconductor device as recited in claim 16 , wherein the n-type layer includes a carrier concentration of between about 1×10 21 cm −3 to about 5×10 21 cm −3 .

19. The semiconductor device as recited in claim 16 , wherein the n-type layer forms one of source and drain regions for a field effect transistor or a diode junction.

20. The semiconductor device as recited in claim 16 , wherein the electronic device includes an on/off ratio of greater than 1×10 3 .

Assignees

• IBM

Inventors

• De Souza Joel P
• Kim Jeehwan
• Sadana Devendra K
• Wacaser Brent A

Classifications

• H10D62/864

  further characterised by the dopants · CPC title

• H10D62/149

  Source or drain regions of field-effect devices · CPC title

• H10D62/86

  being Group II-VI materials, e.g. ZnO · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title