Method of manufacturing a semiconductor package having conductive pillars
US-2024387343-A1 · Nov 21, 2024 · US
Treating the bond pad before connecting, e.g. by applying flux or cleaning
Treating the bond pad before connecting, e.g. by applying flux or cleaning · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W72/07211 |
| Official title | {Treating the bond pad before connecting, e.g. by applying flux or cleaning} |
| Display label | Treating the bond pad before connecting, e.g. by applying flux or cleaning |
| Total patents | 594 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 54 |
| 2016 | 55 |
| 2017 | 78 |
| 2018 | 67 |
| 2019 | 62 |
| 2020 | 45 |
| 2021 | 59 |
| 2022 | 50 |
| 2023 | 40 |
| 2024 | 52 |
| 2025 | 25 |
| 2026 | 7 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Integrated circuit cooling apparatus
US-9472483-B2 · Oct 18, 2016 · US
Systems and methods for determining and adjusting a level of parallelism related to bonding of semiconductor elements
US-9425163-B2 · Aug 23, 2016 · US
Flux and method of manufacturing electronic device
US-2016228999-A1 · Aug 11, 2016 · US
Electrical apparatus and method for manufacturing the same
US-2016133595-A1 · May 12, 2016 · US
Electronic module having an oxide surface finish as a solder mask, and method of manufacturing electronic module using organic solderability preservative and oxide surface finish processes
US-2016064252-A1 · Mar 3, 2016 · US
Systems and methods for determining and adjusting a level of parallelism related to bonding of semiconductor elements
US-2015380380-A1 · Dec 31, 2015 · US
Thermocompression bonders, methods of operating thermocompression bonders, and interconnect methods for fine pitch flip chip assembly
US-2015382480-A1 · Dec 31, 2015 · US
Method and apparatus for connecting packages onto printed circuit boards
US-9224678-B2 · Dec 29, 2015 · US
3D bond and assembly process for severely bowed interposer die
US-9224712-B2 · Dec 29, 2015 · US
Electronic component mounting device
US-9210836-B2 · Dec 8, 2015 · US
Three dimensional integrated circuits stacking approach
US-9209156-B2 · Dec 8, 2015 · US
Semiconductor device having trench adjacent to receiving area and method of forming the same
US-2015348923-A1 · Dec 3, 2015 · US
Method of Forming Solder Bump, and Solder Bump
US-2015333027-A1 · Nov 19, 2015 · US
Pick-and-Place Tool for Packaging Process
US-2015333033-A1 · Nov 19, 2015 · US
Chip packaging structures and treatment methods thereof
US-2015325544-A1 · Nov 12, 2015 · US
Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
US-2015325546-A1 · Nov 12, 2015 · US
Cooling apparatus for an integrated circuit
US-9184112-B1 · Nov 10, 2015 · US
Methods and apparatus for bump-on-trace chip packaging
US-9165796-B2 · Oct 20, 2015 · US
Elongated bump structures in package structure
US-9159695-B2 · Oct 13, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W72/07211?
- CPC H10W72/07211 is the Cooperative Patent Classification code for “Treating the bond pad before connecting, e.g. by applying flux or cleaning.”
- How many patents are filed under CPC H10W72/07211 (Treating the bond pad before connecting, e.g. by applying flux or cleaning)?
- Our database includes 594 publications tagged with this CPC code.
- Is patent activity under CPC H10W72/07211 growing?
- Publication counts under this code: 52 in 2024 vs 25 in 2025 (latest complete years).