Memory management method and apparatus

Patent metadata

Field	Value
Publication number	US-2016335185-A1
Application number	US-201415107255-A
Country	US
Kind code	A1
Filing date	Dec 30, 2014
Priority date	Dec 31, 2013
Publication date	Nov 17, 2016
Grant date	—

Abstract

A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional ( 2 D) data, and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width.

First claim

1 . A memory management method comprising:
determining a stride value for stride access by referring to a size of two-dimensional (2D) data; and allocating neighboring data in a vertical direction of the 2D data to a plurality of banks that are different from one another according to the determined stride value.

2 . The memory management method of claim 1 , wherein the stride value is an odd-number multiple of a data width of the bank, the size of the 2D data corresponds to a number of columns of the 2D data.

3 . The memory management method of claim 2 , wherein the stride value is determined to satisfy the following equation:
stride= a× 2 n ≧the number of columns of the 2 D data,
wherein “a” is a positive odd number, “2n” is a bank width, and “n” is a natural number.

4 . The memory management method of claim 1 , wherein, as the neighboring data are allocated to the plurality of banks that are different from one another, the neighboring data are simultaneously loaded or stored.

5 . The memory management method of claim 1 , wherein the stride value is a distance between the plurality of banks to which the neighboring data are allocated.

6 . The memory management method of claim 1 , wherein a maximum number of the neighboring data in the vertical direction that are available for stride access is equal to the number of the plurality of banks.

7 . The memory management method of claim 1 , further comprising generating an offset value of each of the plurality of banks according to a bank to which first data of the neighboring 2D data is allocated and the determined stride value.

8 . The memory management method of claim 7 , further comprising calculating an address of each of the plurality of banks by using one of the generated offset values.

9 . The memory management method of claim 1 , further comprising:
receiving a stride access request for the neighboring data allocated to the plurality of banks that are different from one another; rearranging an order in which data is loaded from the different banks based on an address of each of the plurality of banks and the stride value; and outputting rearranged data.

10 . The memory management method of claim 9 , further comprising:
storing the rearranged data in a cache and setting validity of the cache; storing an address of each of the plurality of banks as an address tag; and loading data from the cache when a next stride access request is received and the address of each of the plurality of banks that are different from one another is identical to the stored address tag.

11 . The memory management method of claim 10 , further comprising:
storing data corresponding to the address of each of the plurality of banks that are different from one another when the address of each of the plurality of banks that are different from one another is not identical to the stored address tag; setting validity of the cache and storing the address of each bank as an address tag; and selecting a memory output according to the next stride access request.

12 . A memory management method comprising:
receiving a stride access request for neighboring data in a vertical direction that are stored in a plurality of banks that are different from one another; loading the neighboring data in the vertical direction from each of the plurality of banks that are different from one another according to a bank address corresponding to a received stride access request; and storing, in a cache, data that is stored in each of the plurality of banks that are different from one another and corresponds to the bank address, while outputting loaded data.

13 . A memory management apparatus for managing data of a memory configured with a plurality of banks,
the memory management apparatus is configured to: determine a stride value for stride access by referring to a size of two-dimensional (2D) data and allocate neighboring data in a vertical direction of the 2D data to the plurality of banks that are different from one another according to the determined stride value.

14 . The memory management apparatus of claim 13 , wherein the stride value is an odd-number multiple of a data width of the bank, and the size of the 2D data corresponds to a number of columns of the 2D data.

15 . The memory management apparatus of claim 14 , wherein the stride value is determined to satisfy the following equation:
stride= a× 2 n ≧the number of columns of the 2 D data,
wherein “a” is a positive odd number, “2n” is a bank width, and “n” is a natural number.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kwon Ki-Seok
• Park Chul-Soo
• Kim Suk-Jin

Classifications

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0851 Primary

  Cache with interleaved addressing · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0886

  Variable-length word access · CPC title

• G06F12/0207 Primary

  with multidimensional access, e.g. row/column, matrix · CPC title