System including hierarchical memory modules having different types of integrated circuit memory devices

Patent metadata

Field	Value
Publication number	US-9767918-B2
Application number	US-201615282932-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Mar 30, 2007
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.

First claim

What is claimed is:

1. A system comprising:
a plurality of volatile memory devices disposed on a first memory module that is coupled to a memory controller by a first signal path;
a nonvolatile memory device disposed on a second memory module that is coupled to the first memory module by a second signal path, wherein a memory transaction for the nonvolatile memory device is transferred from the memory controller to at least one of the plurality of volatile memory devices using the first signal path, and wherein data associated with the memory transaction is to be written from the at least one of the plurality of volatile memory devices to the nonvolatile memory device using the second signal path and a control signal; and
a defect circuit to generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.

2. The system of claim 1 , wherein the defect circuit is further to store an address corresponding to the memory location when the defect is detected.

3. The system of claim 1 , further comprising:
a mapping circuit to receive the memory location and the control signal and to assign a new memory location for the data associated with the memory transaction based on the control signal.

4. The system of claim 1 , wherein the test value is associated with a random based number or is based on content of another memory location.

5. The system of claim 1 , wherein the memory location is not used to store subsequent data when the comparison of the test value read from the memory location to the stored value indicates the detection of the defect.

6. The system of claim 1 , further comprising:
a clock circuit to generate a clock signal associated with the data that is to be written from the at least one of the plurality of volatile memory devices to the nonvolatile memory device.

7. The system of claim 1 , wherein the plurality of volatile memory devices and the nonvolatile memory device are in a daisy-chained configuration.

8. A method comprising:
receiving a memory transaction for a memory system comprising a plurality of volatile memory devices disposed on a first memory module that is coupled to a memory controller by a first signal path and a nonvolatile memory device disposed on a second memory module that is coupled to the first memory module by a second signal path;
transferring data associated with the memory transaction from the memory controller to at least one of the plurality of volatile memory devices by using the first signal path;
generating a control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location of the nonvolatile memory device to a stored value; and
transferring data associated with the memory transaction from the at least one of the plurality of volatile memory devices to the nonvolatile memory device by using the second signal path and the control signal.

9. The method of claim 8 , further comprising:
storing an address corresponding to the memory location when the defect is detected.

10. The method of claim 8 , further comprising:
assigning a new memory location for the data associated with the memory transaction based on the control signal.

11. The method of claim 8 , wherein the test value is associated with a random based number or is based on content of another memory location.

12. The method of claim 8 , wherein the memory location is not used to store subsequent data when the comparison of the test value read from the memory location to the stored value indicates the detection of the defect.

13. The method of claim 8 , further comprising:
generating a clock signal associated with the data that is to be written from the at least one of the plurality of volatile memory devices to the nonvolatile memory device.

14. The method of claim 8 , wherein the plurality of volatile memory devices and the nonvolatile memory device are in a daisy-chained configuration.

15. A circuit comprising:
a plurality of volatile memory devices disposed on a first memory module that is coupled to a memory controller by a first signal path;
an interface to a nonvolatile memory device disposed on a second memory module that is coupled to the first memory module by a second signal path, wherein a memory transaction for the nonvolatile memory device is transferred from the memory controller to at least one of the plurality of volatile memory devices using the first signal path, and wherein data associated with the memory transaction is to be written from the at least one of the plurality of volatile memory devices to the nonvolatile memory device using the second signal path and a control signal; and
a defect circuit to generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.

16. The circuit of claim 15 , wherein the defect circuit is further to store an address corresponding to the memory location when the defect is detected.

17. The circuit of claim 15 , further comprising:
a mapping circuit to receive the memory location and the control signal and to assign a new memory location for the data associated with the memory transaction based on the control signal.

18. The circuit of claim 15 , wherein the test value is associated with a random based number or is based on content of another memory location.

19. The circuit of claim 15 , wherein the memory location is not used to store subsequent data when the comparison of the test value read from the memory location to the stored value indicates the detection of the defect.

20. The circuit of claim 15 , further comprising:
a clock circuit to generate a clock signal associated with the data that is to be written from the at least one of the plurality of volatile memory devices to the nonvolatile memory device.

Assignees

• Rambus Inc

Inventors

• Hampel Craig
• Horowitz Mark

Classifications

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G11C29/32

  Serial access; Scan testing · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic