Method and apparatus to use DRAM as a cache for slow byte-addressible memory for efficient cloud applications
US-12174739-B2 · Dec 24, 2024 · US
US2016232091A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016232091-A1 |
| Application number | US-201514619628-A |
| Country | US |
| Kind code | A1 |
| Filing date | Feb 11, 2015 |
| Priority date | Feb 11, 2015 |
| Publication date | Aug 11, 2016 |
| Grant date | — |
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Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.
Opening claim text (preview).
What is claimed is: 1 . A method of selecting from among a plurality of shared cache memories a remote shared cache memory to use as a victim cache, comprising: identifying among the plurality of shared cache memories those remote shared cache memories with space available for use as the victim cache; retrieving, for each of the identified remote shared cache memories or a processor cluster associated with each of the identified remote shared cache memories, data relating to a metric for selecting a remote shared cache memory as the victim cache; determining a suitability of each of the identified remote shared cache memories for use as the victim cache based on the metric; and selecting one of the identified remote shared cache memories to use as the victim cache based on the determination. 2 . The method of claim 1 , wherein: the metric for selecting a remote shared cache memory as the victim cache comprises a performance speed metric; retrieving, for each of the identified remote shared cache memories or a processor cluster associated with each of the identified remote shared cache memories, data relating to a metric for selecting a remote shared cache memory as the victim cache comprises retrieving a hit rate of the identified remote shared cache memory, a miss rate for the identified remote shared cache memory, a latency of the processor cluster, and a latency for a main memory; and determining a suitability of each of the identified remote shared cache memories for use as the victim cache based on the metric comprises: calculating a performance speed indicator for the identified remote shared cache memory; and comparing the performance speed indicator for the identified remote shared cache memory to a threshold or another performance speed indicator for another identified remote shared cache memory. 3 . The method of claim 2 , further comprising interleaving memory addresses of the identified remote shared cache memory selected for use as the victim cache with another remote shared cache memory selected for use as the victim cache based on an address interleaving scheme. 4 . The method of claim 2 , wherein calculating a performance speed indicator for the identified remote shared cache memory comprises using the equation: the hit rate of the identified remote shared cache memory times the latency of the processor cluster plus the miss rate of the identified remote shared cache memory times the latency of the main memory. 5 . The method of claim 1 , wherein: the metric for selecting a remote shared cache memory as the victim cache comprises an efficiency metric; retrieving, for each of the identified remote shared cache memories or a processor cluster associated with each of the identified remote shared cache memories, data relating to a metric for selecting a remote shared cache memory as the victim cache comprises retrieving state data of the processor cluster; and determining a suitability of each of the identified remote shared cache memories for use as the victim cache based on the metric comprises comparing the state data of the processor cluster to a threshold or state data of another processor cluster. 6 . The method of claim 5 , further comprising interleaving memory addresses of the identified remote shared cache memory selected for use as the victim cache with another remote shared cache memory selected for use as the victim cache based on an address interleaving scheme. 7 . The method of claim 5 , wherein retrieving state data of the processor cluster comprises retrieving at least one of a temperature, a current leakage, a power usage, or an operation frequency. 8 . The method of claim 1 , wherein: the metric for selecting a remote shared cache memory as the victim cache comprises an effective victim cache size metric; retrieving, for each of the identified remote shared cache memories or a processor cluster associated with each of the identified remote shared cache memories, data relating to a metric for selecting a remote shared cache memory as the victim cache comprises retrieving at least one of an available shared cache memory size of the identified remote shared cache memory or a memory latency for the identified remote shared cache memory; and determining a suitability of each of the identified remote shared cache memories for use as the victim cache based on the metric comprises comparing at least one of the available shared cache memory size of the identified remote shared cache memory or the memory latency for the identified remote shared cache memory to a threshold or a same type of data for another identified remote shared cache memory. 9 . The method of claim 8 , further comprising interleaving memory addresses of the identified remote shared cache memory selected for use as the victim cache with another remote shared cache memory selected for use as the victim cache based on an address interleaving scheme. 10 . The method of claim 9 , further comprising: determining the address interleaving scheme based on a ratio of available shared cache memory size between the identified remote shared cache memory and other remote shared cache memory or a ratio of memory latency between the identified remote shared cache memory and the other remote shared cache memory, wherein the address interleaving scheme includes one of an arbitrary address interleaving scheme, a symmetrical n-way address interleaving scheme, and an asymmetrical address interleaving scheme. 11 . The method of claim 1 , further comprising determining the metric for selecting a remote shared cache memory as the victim cache. 12 . A computing device, comprising: a plurality of processor clusters communicatively connected to each other; a first processor cluster of the plurality of processor clusters assigned an execution process; a plurality of shared cache memories each communicatively connected to at least one of the plurality of processor clusters; and a processor communicatively connected to the plurality of processor clusters and configured with processor-executable instructions to perform operations comprising: identifying among the plurality of shared cache memories those remote shared cache memories with space available for use as a victim cache; retrieving, for each of the identified remote shared cache memories or a processor cluster associated with each of the identified remote shared cache memories, data relating to a metric for selecting a remote shared cache memory as the victim cache; determining a suitability of each of the identified remote shared cache memories for use as the victim cache based on the metric; and selecting one of the identified remote shared cache memories to use as the victim cache based on the determination. 13 . The computing device of claim 12 , further comprising a main memory communicatively connected to the processor, wherein: the metric for selecting a remote shared cache memory as the victim cache comprises a performance speed metric; and the processor is further configured with processor-executable instructions to perform operations such that: retrieving, for each of the identified remote shared cache memories or a processor cluster associated with each of the identified remote shared cache memories, data relating to a metric for selecting a remote shared cache memory as the victim cache comprises retrieving a hit rate of the identified remote shared cache memory, a miss rate for the identified remote shared cache memory, a latency of the processor cluster, and a latency for the main memory; and determining a suitability of each of the identified remote shared cache memorie
with a shared cache · CPC title
with dedicated cache, e.g. instruction or stack · CPC title
with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title
Cache with interleaved addressing · CPC title
Hit rate improvement · CPC title
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