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Semiconductor Device Having a Copper Element and Method of Forming a Semiconductor Device Having a Copper Element
US2016329263A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016329263-A1 |
| Application number | US-201615217383-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 22, 2016 |
| Priority date | Dec 9, 2011 |
| Publication date | Nov 10, 2016 |
| Grant date | — |
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- Title
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Abstract
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A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device, comprising: a base element; and a copper element over the base element, the copper element comprising a layer stack including at least two copper layers and at least one intermediate conductive layer of a material different from copper, the at least two copper layers and the at least one intermediate conductive layer being alternately stacked over each other. 2 . The semiconductor device of claim 1 , wherein each of the at least two copper layers has a thickness of less than 5 μm. 3 . The semiconductor device of claim 1 , wherein each of the at least one intermediate layer has a thickness of less than 30 nm. 4 . The semiconductor device of claim 1 , further comprising a cover layer comprising at least one of NiP, NiMoP, NiPd, Ni(X)P, and Ni(X,Y)P, wherein X and Y denote further elements. 5 . The semiconductor device of claim 1 , wherein the copper element is a layer, a patterned layer or a wiring. 6 . A semiconductor device, comprising: a semiconductor substrate; components of a power device disposed in the semiconductor substrate; and a copper element over the semiconductor substrate and electrically connected to one of the components, the copper element comprising a layer stack including at least two copper layers and at least one intermediate conductive layer of a material different from copper, the at least two copper layers and the at least one intermediate conductive layer being alternately stacked over each other. 7 . The semiconductor device of claim 6 , wherein each of the at least two copper layers has a thickness of less than 5 μm. 8 . The semiconductor device of claim 6 , wherein each of the at least one intermediate layer has a thickness of less than 30 nm. 9 . The semiconductor device of claim 6 , further comprising a cover layer comprising at least one of NiP, NiMoP, NiPd, Ni(X)P, and Ni(X,Y)P, wherein X and Y denote further elements. 10 . The semiconductor device of claim 6 , wherein the copper element is a layer, a patterned layer or a wiring. 11 . The semiconductor device of claim 6 , wherein the power device is a power transistor. 12 . A method of manufacturing a semiconductor device, the method comprising: forming a copper element over a base element, by forming a layer stack including at least two copper layers and at least one intermediate conductive layer of a material different from copper, the at least two copper layers and the at least one intermediate conductive layer being alternately stacked over each other. 13 . The method of claim 12 , wherein each of the at least two copper layers has a thickness of less than 5 pm. 14 . The method of claim 12 , wherein each of the at least one intermediate layer has a thickness of less than 30 nm. 15 . The method of claim 12 , further comprising: forming a cover layer comprising at least one of NiP, NiMoP, NiPd, Ni(X)P, and Ni(X,Y)P, wherein X and Y denote further elements.
Assignees
Inventors
Classifications
Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title
Assembling together parts thereof · CPC title
- H10W20/425Primary
Barrier, adhesion or liner layers · CPC title
- H10W40/255Primary
having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title
- H01L23/3735Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2016329263A1 cover?
- A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
- Who is the assignee on this patent?
- Infineon Technologies Ag
- What technology area does this patent fall under?
- Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 10 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).