Semiconductor structures having low resistance paths throughout a wafer
US-2015332925-A1 · Nov 19, 2015 · US
US2016307759A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016307759-A1 |
| Application number | US-201615098624-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 14, 2016 |
| Priority date | Apr 16, 2015 |
| Publication date | Oct 20, 2016 |
| Grant date | — |
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A plating method includes forming a catalyst layer 118 on a surface of a substrate including an inner surface of a recess 112; drying the substrate having the catalyst layer formed thereon such that an inside of the recess is dried as well; removing the catalyst layer at least on the surface of the substrate at the outside of the recess by supplying a processing liquid, which is configured to dissolve a material of the surface of the substrate, onto the surface of the substrate while rotating the dried substrate and while preventing or suppressing the processing liquid from being introduced into the dried inside of the recess; and forming a plating layer 119 on the inside of the recess, at which the catalyst layer is not removed, by an electroless plating process.
Opening claim text (preview).
We claim: 1 . A plating method comprising: preparing a substrate having a recess formed on a surface thereof; forming a catalyst layer on the surface of the substrate including an inner surface of the recess; drying the substrate having the catalyst layer formed thereon such that an inside of the recess is dried as well; removing the catalyst layer at least on the surface of the substrate at the outside of the recess by supplying a processing liquid, which is configured to dissolve a material of the surface of the substrate, onto the surface of the substrate while rotating the dried substrate and while preventing or suppressing the processing liquid from being introduced into the dried inside of the recess; and forming a plating layer on the inside of the recess, at which the catalyst layer is not removed, by an electroless plating process. 2 . The plating method of claim 1 , wherein the forming of the catalyst layer comprises: attaching a metal catalyst ion to the surface of the substrate by supplying a catalyst solution containing the metal catalyst ion onto the substrate; and reducing the metal catalyst ion into a metal. 3 . The plating method of claim 2 , wherein the metal is palladium. 4 . The plating method of claim 1 , wherein the plating layer is made of NiB. 5 . The plating method of claim 1 , wherein the processing liquid is dilute hydrofluoric acid, and the material of the surface of the substrate is silicon or a silicon compound allowed to be dissolved by the dilute hydrofluoric acid. 6 . The plating method of claim 1 , wherein the material of the surface of the substrate is a resist, and the processing liquid is a solvent configured to dissolve the resist. 7 . A computer-readable recording medium having stored thereon computer executable instructions that, in response to execution, cause a plating system to perform a plating method as claimed in claim 1 . 8 . A plating system comprising: a first pre-treatment unit configured to form a catalyst layer on a surface of a substrate, which has a recess on the surface thereof, including an inner surface of the recess and configured to dry the substrate having the catalyst layer formed thereon such that an inside of the recess is dried as well; a second pre-treatment unit configured to remove the catalyst layer at least on the surface of the substrate at the outside of the recess by supplying a processing liquid, which is configured to dissolve a material of the surface of the substrate, onto the surface of the substrate while rotating the dried substrate and while preventing or suppressing the processing liquid from being introduced into the dried inside of the recess; and a plating unit configured to form a plating layer on the inside of the recess, at which the catalyst layer is not removed, by an electroless plating process.
by chemical means · CPC title
the processing being the formation of vias or contact holes · CPC title
during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title
based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title
by selectively depositing, e.g. by using selective CVD or plating · CPC title
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