Memory system, semiconductor memory device, and wiring substrate, the semiconductor memory device including termination resistance circuit or control circuit
US-9001597-B2 · Apr 7, 2015 · US
US9214939B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9214939-B2 |
| Application number | US-201414328656-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 10, 2014 |
| Priority date | Dec 2, 2013 |
| Publication date | Dec 15, 2015 |
| Grant date | Dec 15, 2015 |
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Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.
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What is claimed is: 1. An adaptive digital signal bus termination apparatus, comprising: a plurality of termination switches, each termination switch to be singly coupled in series with a bus signal conductor at a receiver end of a digital signal bus furthest from a driver end of the digital signal bus, the termination switch configured to leave the bus signal conductor electrically open at the receiver end of the bus when the termination switch is open; a plurality of variable…
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