High thermal budget magnetic memory

Patent metadata

Field	Value
Publication number	US-2016276407-A1
Application number	US-201615071180-A
Country	US
Kind code	A1
Filing date	Mar 15, 2016
Priority date	Mar 16, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell. A bottom electrode and a fixed layer are formed. The fixed layer includes a composite spacer layer disposed on the bottom electrode. The composite spacer layer includes a base layer and an amorphous buffer layer disposed over the base layer. A reference layer is disposed on the composite spacer layer. The amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation. At least one tunneling barrier layer is formed over the fixed layer. A storage layer is formed over the tunneling barrier layer and a top electrode is formed over the storage layer.

First claim

What is claimed is:

1 . A method of forming a memory cell comprising:
forming a select unit on a substrate, wherein the select unit comprises a transistor having
a first source/drain (S/D) region,
a second S/D region, and
a gate between the first and second S/D regions;
forming a dielectric layer on the substrate covering the select unit, wherein the dielectric layer includes storage pad coupled to the first S/D region; forming a storage unit on the storage pad, wherein forming the storage unit comprises
forming a bottom electrode,
forming a fixed layer on the bottom electrode, wherein the fixed layer comprises
a composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprises
a base layer, and
an amorphous buffer layer disposed over the base layer, and

a reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation,

forming at least one tunneling barrier layer over the fixed layer,
forming a storage layer over the tunneling barrier layer, and
forming a top electrode over the storage layer; and
forming a bitline coupled to the top electrode layer.

2 . The method of claim 1 wherein:
the fixed layer further comprises a hard layer disposed on the bottom electrode;
the base layer is disposed on the hard layer and the base layer comprises Mo; and the
amorphous buffer layer disposed over the base layer is a metal layer (M), forming a composite spacer layer Mo/M and the amorphous buffer layer serves as a template for the reference layer to have a body-centered cubic (BCC) crystalline structure in the (001) orientation.

3 . The method of claim 2 wherein the metal layer comprises a metal material that serves as a template for the reference layer to have high tunnel magnetoresistance (TMR).

4 . The method of claim 3 wherein the metal layer M comprises Ta, V, FeV, TaN or MoN.

5 . The method of claim 2 wherein the hard layer comprises Co/Pt bilayer and the reference layer comprises CoFeB layer.

6 . The method of claim 2 wherein forming the composite spacer layer further comprises forming a coupling layer (C) in between the base layer and buffer layer, wherein the coupling layer provides strong coupling between the hard layer and the reference layer.

7 . The method of claim 6 wherein the amorphous buffer layer disposed over the base layer is a metal layer (M), forming a composite spacer layer Mo/C/M.

8 . The method of claim 7 wherein the coupling layer is a magnetic layer which is ferromagnetically weak which acts as a paramagnetic layer to promote strong magnetic coupling between the hard layer and the reference layer.

9 . The method of claim 8 wherein the magnetic layer of the coupling layer includes Co, Fe or Ni.

10 . The method of claim 6 wherein the hard layer comprises Co/Pt bilayer and the reference layer comprises CoFeB layer.

11 . The method of claim 1 wherein the tunneling barrier layer comprises first and second tunneling barrier layers and wherein the storage layer is formed in between the first and second tunneling barrier layers.

12 . A method of forming a storage unit of a magnetic memory cell comprising:
forming a bottom electrode; forming a fixed layer on the bottom electrode, wherein the fixed layer comprises
a composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprises
a base layer, and
an amorphous buffer layer disposed over the base layer, and

a reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation;
forming at least one tunneling barrier layer over the fixed layer; forming a storage layer over the tunneling barrier layer; and forming a top electrode over the storage layer.

13 . The method of claim 12 wherein:
the fixed layer further comprises a hard layer; and
the composite spacer layer is disposed on the hard layer and serves as a diffusion barrier between the reference and hard layers.

14 . The method of claim 12 wherein:
the base layer comprises Mo; and
the amorphous buffer layer disposed over the base layer is a metal layer (M), forming a composite spacer layer Mo/M and the amorphous buffer layer serves as a template for the reference layer to have a body-centered cubic (BCC) crystalline structure in the (001) orientation.

15 . The method of claim 14 wherein the metal layer comprises a metal material that serves as a template for the reference layer to have high tunnel magnetoresistance (TMR).

16 . The method of claim 13 wherein forming the composite spacer layer further comprises forming a coupling layer between the base layer and buffer layer, wherein the coupling layer provides strong coupling between the hard layer and the reference layer.

17 . The method of claim 16 wherein the coupling layer is a magnetic layer which is ferromagnetically weak which acts as a paramagnetic layer to promote strong magnetic coupling between the hard layer and the reference layer.

18 . A storage unit of a magnetic memory cell comprising:
a bottom electrode; a fixed layer disposed on the bottom electrode, wherein the fixed layer comprises
a composite spacer layer disposed on the bottom electrode, wherein the composite spacer layer comprises
a base layer, and
an amorphous buffer layer disposed over the base layer, and

a reference layer on the composite spacer layer, wherein the amorphous buffer layer serves as a template for the reference layer to have a desired crystalline structure in a desired orientation;
at least one tunneling barrier layer disposed over the fixed layer; a storage layer disposed over the tunneling barrier layer; and a top electrode disposed over the storage layer.

19 . The storage unit of claim 18 wherein:
the fixed layer further comprises a hard layer;
the base layer is disposed on the hard layer and the base layer comprises Mo; and
the amorphous buffer layer disposed over the base layer is a metal layer (M), forming a composite spacer layer Mo/M and the amorphous buffer layer serves as a template for the reference layer to have a body-centered cubic (BCC) crystalline structure in the (001) orientation.

20 . The storage unit of claim 19 wherein the composite spacer layer further comprises a coupling layer disposed between the base layer and buffer layer, wherein the coupling layer provides strong coupling between the hard layer and the reference layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Naik Vinayak Bharat
• Lee Kangho
• Tahmasebi Taiebeh
• Wang Chenchen Jacob

Classifications

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title

• H10D30/0223

  having source and drain regions or source and drain extensions self-aligned to sides of the gate · CPC title

• H10D30/027

  of lateral single-gate IGFETs · CPC title

• H01L43/10

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title