Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016268263-A1
Application number	US-201514734140-A
Country	US
Kind code	A1
Filing date	Jun 9, 2015
Priority date	Mar 11, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source layer formed over the substrate, a second source layer formed over the first source layer, a reinforcement pattern formed in the second source layer, a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern, channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer, and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate in which a cell region and contact regions located at both sides of the cell region are defined; a first source layer formed over the substrate; a second source layer formed over the first source layer; a reinforcement pattern formed in the second source layer; a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern; channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer; and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.

2 . The semiconductor device of claim 1 , wherein the isolation insulating pattern is located above and overlaps the reinforcement pattern.

3 . The semiconductor device of claim 1 , wherein the reinforcement pattern includes line patterns located at boundaries of the cell region and the contact regions.

4 . The semiconductor device of claim 1 , wherein the reinforcement pattern includes a line pattern located in the cell region or the contact regions.

5 . The semiconductor device of claim 4 , wherein the isolation insulating pattern overlaps the line pattern located in the cell region.

6 . The semiconductor device of claim 1 , wherein the reinforcement pattern includes island patterns located adjacent to a boundary between neighboring memory blocks.

7 . The semiconductor device of claim 1 , wherein the reinforcement pattern includes an insulating material.

8 . The semiconductor device of claim 1 , further comprising:
slit insulating layers passing through the stacked structure to contact the second source layer and not overlap the reinforcement pattern.

9 . The semiconductor device of claim 1 , further comprising:
memory layers interposed between the channel layers and the stacked structure.

10 . The semiconductor device of claim 1 , wherein the second source layer is formed on surfaces of the channel layers and a surface of the first source layer to define a concave portion in a surface of the second source layer.

11 . The semiconductor device of claim 10 , further comprising:
a slit insulating layer filling the concave portion of the second source layer.

12 . The semiconductor device of claim 11 , further comprising:
a gap formed in the slit insulating layer.

13 . The semiconductor device of claim 1 , further comprising:
a slit passing through the stacked structure; a slit insulating layer formed on a sidewall of the slit, wherein a central portion of the slit is opened by the slit insulating layer; and a common source line filling the central portion of the slit and contacting the second source layer.

14 . The semiconductor device of claim 1 , further comprising:
a data storage layer arranged between each of the channel layers and the stacked structure; and an etch barrier layer formed between the reinforcement pattern and the stacked structure.

15 . The semiconductor device of claim 14 , wherein the etch barrier layer has a greater thickness than the data storage layer.

Assignees

• Sk Hynix Inc

Inventors

• Lee Ki Hong
• Pyi Seung Ho

Classifications

• H01L27/115 Primary

  Electricity · mapped topic

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title