Vertical memory devices and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9276133-B2
Application number	US-201414184262-A
Country	US
Kind code	B2
Filing date	Feb 19, 2014
Priority date	May 13, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.

First claim

What is claimed is:

1. A method for manufacturing a vertical memory device, the method comprising:
alternately stacking a plurality of insulation layers and a plurality of first sacrificial layers on a substrate;
forming a plurality of holes through the plurality of insulation layers and first sacrificial layers;
performing a plasma treatment process to oxidize the first sacrificial layers exposed by the holes;
forming a plurality of second sacrificial layer patterns projecting from sidewalls of the holes in response to performing the plasma treatment process;
forming a blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern on the sidewall of the holes that cover the second sacrificial layer patterns;
forming a plurality of channels to fill the holes;
removing the first sacrificial layers and the second sacrificial layer patterns to form a plurality of gaps exposing a sidewall of the blocking layer pattern; and
forming a plurality of gate electrodes to fill the gaps.

2. The method of claim 1 , wherein portions of the second sacrificial layer patterns extending from the sidewalls of the holes have different widths relative to each other.

3. The method of claim 2 , wherein the widths of the second sacrificial layer pattern portions become gradually smaller from a top portion to a bottom portion of the holes.

4. The method of claim 3 , wherein a ratio between a first width of the second sacrificial layer pattern closest to the substrate and a second width of the second sacrificial layer pattern farmost from the substrate is smaller than about 1/5.

5. The method of claim 3 , wherein the plasma treatment process is performed at a pressure below about 1 Torr.

6. The method of claim 1 , wherein the plasma treatment process uses an oxygen gas, a nitrogen oxide gas, a nitrous oxide gas, an ozone gas, a water gas or a mixture thereof.

7. The method of claim 1 , further comprising forming a semiconductor pattern partially filling the holes, before performing the plasma treatment process.

8. The method of claim 1 , further comprising:
forming a preliminary semiconductor pattern that at least partially fills the holes, before performing the plasma treatment process; and
partially removing the preliminary semiconductor pattern to form a semiconductor pattern, after performing the plasma treatment process.

9. A method of manufacturing a vertical memory device, the method comprising:
alternately stacking a plurality of insulation layers and a plurality of first sacrificial layers on a substrate;
partially removing the insulation layers and the first sacrificial layers to form a plurality of preliminary holes;
performing a plasma treatment process to oxidize the first sacrificial layers exposed by the preliminary holes;
forming a plurality of second sacrificial layer patterns projecting from sidewalls of the preliminary holes in response to performing the plasma treatment process;
partially removing the insulation layers and the first sacrificial layers under the preliminary holes to form a plurality of holes;
forming a blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern on the sidewall of the holes that cover the second sacrificial layer patterns;
forming a plurality of channels to fill the holes;
removing the first sacrificial layer and the second sacrificial layer patterns to form a plurality of gaps exposing a sidewall of the blocking layer pattern; and
forming a plurality of gate electrodes to fill the gaps.

10. The method of claim 9 , wherein the widths of the second sacrificial layer patterns becomes gradually smaller from a top portion to a bottom portion of the preliminary holes.

11. The method of claim 10 , wherein a ratio between a first width of the second sacrificial layer pattern closest to the substrate and a second width of the second sacrificial layer pattern farmost from the substrate is smaller than about 1/5.

12. A method for forming a vertical memory device, the method comprising:
alternately stacking a plurality of insulation layers and a plurality of first sacrificial layers on a substrate;
forming a plurality of holes through the plurality of insulation layers and first sacrificial layers;
forming a plurality of second sacrificial layer patterns, wherein portions of the second sacrificial layer patterns project from sidewalls of the holes;
forming a charge storing structure at the holes;
removing the first sacrificial layers and the second sacrificial layer patterns to form a plurality of gaps exposing a sidewall of the charge storing structure; and
forming a plurality of gate electrodes to fill the gaps, wherein a variation of widths of the holes are offset by widths of the portions of the second sacrificial layer pattern projecting the sidewalls of the holes.

13. The method of claim 12 , wherein forming the second sacrificial layer patterns comprises:
performing a plasma treatment process to oxidize the first sacrificial layers exposed by the holes.

14. The method of claim 12 , wherein portions of the second sacrificial layer patterns extending from the sidewalls of the holes have different widths relative to each other.

15. The method of claim 14 , wherein the widths of the second sacrificial layer pattern portions become gradually smaller from a top portion to a bottom portion of the holes.

16. The method of claim 12 , wherein a ratio between a first width of the second sacrificial layer pattern closest to the substrate and a second width of the second sacrificial layer pattern farmost from the substrate is smaller than about 1/5.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jung-Hwan
• Yang Jun-Kyu
• Lim Hun-Hyeong
• Choi Jae-Ho
• Hwang Ki-Hyun

Classifications

• H10D64/687

  having cavities, e.g. porous gate dielectrics having gasses therein · CPC title

• H10D30/689 Primary

  Vertical floating-gate IGFETs · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title