Nonvolatile semiconductor memory device and method for manufacturing same

US9111964B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9111964-B2
Application numberUS-201314019798-A
CountryUS
Kind codeB2
Filing dateSep 6, 2013
Priority dateMar 19, 2013
Publication dateAug 18, 2015
Grant dateAug 18, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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According one embodiment, a nonvolatile semiconductor memory device, includes: a stacked body, and each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the a stacked body; a first interlayer insulating film on the stacked body; a gate electrode on the first interlayer insulating film; a second interlayer insulating film on the gate electrode; a semiconductor layer extended from an upper end of the second interlayer insulating film to a lower end of the stacked body; a first insulating film between the semiconductor layer and each of the plurality of electrode layers; and a second insulating film between the semiconductor layer and the gate electrode, a thickness of the semiconductor layer provided above an upper end of the gate electrode being thicker than a thickness of the semiconductor layer provided below the upper end of the gate electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A nonvolatile semiconductor memory device, comprising: a foundation layer; a stacked body provided on the foundation layer, and each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; a first interlayer insulating film provided on the stacked body; a gate electrode provided on the first interlayer insulating film; a second interlayer insulating film provided on the gate elect…

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What does patent US9111964B2 cover?
According one embodiment, a nonvolatile semiconductor memory device, includes: a stacked body, and each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the a stacked body; a first interlayer insulating film on the stacked body; a gate electrode on the first interlayer insulating film; a second interlayer insulating film on the gate el…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10D30/0413. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).