Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells

Patent metadata

Field	Value
Publication number	US-9305938-B2
Application number	US-201514824942-A
Country	US
Kind code	B2
Filing date	Aug 12, 2015
Priority date	Nov 18, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

First claim

We claim:

1. A method of fabricating integrated structures, comprising:
forming a metal-containing material over a stack of alternating first and second levels;
forming an opening which extends through the metal-containing material and through the stack of alternating first and second levels;
forming repeating vertically-stacked electrical components along the stack of alternating first and second levels at sidewalls of the opening; and
further comprising removing the metal-containing material from over the stack after forming the opening.

2. The method of claim 1 wherein the opening has an aspect ratio of at least about 40:1.

3. A method of fabricating integrated structures, comprising:
forming a metal-containing material over a stack of alternating first and second levels;
forming an opening which extends through the metal-containing material and through the stack of alternating first and second levels;
forming repeating vertically-stacked electrical components along the stack of alternating first and second levels at sidewalls of the opening; and
wherein:
the repeating vertically-stacked electrical components comprise a string of memory cells;
the metal-containing material comprises one or both of tungsten nitride and titanium nitride; and
the metal-containing material is incorporated into a drain-side select gate over the string of memory cells.

4. The method of claim 3 wherein:
an electrically conductive material is under the stack of alternating first and second levels;
the opening is extended through the electrically conductive material; and
the electrically conductive material is incorporated into a source-side select gate under the string of memory cells.

5. A method of forming vertically-stacked memory cells, comprising:
forming a metal-containing material over a stack of alternating silicon dioxide levels and conductively-doped silicon levels;
forming a first opening to extend through the metal-containing material and the stack;
forming cavities extending into the conductively-doped silicon levels along sidewalls of the first opening;
forming charge-blocking dielectric and charge-storage structures within the cavities; a second opening remaining after forming the charge-blocking dielectric and the charge-storage structures, the second opening having sidewalls extending along the metal-containing material and the charge-storage structures;
lining the sidewalls of the second opening with gate dielectric; and
forming channel material within the lined second opening.

6. The method of claim 5 wherein the metal-containing material comprises one or more metal nitrides.

7. The method of claim 5 wherein the lining of the sidewalls of the second opening comprises depositing the gate-dielectric material along the sidewalls, or converting polysilicon liner material to gate dielectric through oxidation with steam.

8. The method of claim 5 wherein:
the charge-blocking dielectric and the charge-storage structures are together incorporated into a vertically-extending string of memory cells;
the metal-containing material comprises one or both of tungsten and titanium nitride; and
the metal-containing material is incorporated into a drain-side select gate over the vertically-extending string of memory cells.

9. The method of claim 8 wherein:
an electrically conductive material is under the stack of alternating silicon dioxide levels and conductively-doped silicon levels;
the first opening is extended through the electrically conductive material; and
the electrically conductive material is incorporated into a source-side select gate under the vertically-extending string of memory cells.

Assignees

• Micron Technology Inc

Inventors

• Simsek-Ege Fatma Arzum
• Wilson Aaron R

Classifications

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title