Metal gate and manufacutring method thereof

Patent metadata

Field	Value
Publication number	US-2016211339-A1
Application number	US-201514671053-A
Country	US
Kind code	A1
Filing date	Mar 27, 2015
Priority date	Jan 20, 2015
Publication date	Jul 21, 2016
Grant date	—

Abstract

The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface, wherein a ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.

2 . The semiconductor structure of claim 1 , wherein the at least one of the plurality of metal layers is a work function metal layer.

3 . The semiconductor structure of claim 1 , wherein the thickest portion is over the first surface.

4 . The semiconductor structure of claim 3 , wherein the thinnest portion is at a corner connecting the first surface and the second surface.

5 . The semiconductor structure of claim 1 , wherein the metal gate comprises Al metal layer.

6 . The semiconductor structure of claim 1 , further comprising a high k dielectric layer between the metal gate and the active region.

7 . The semiconductor structure of claim 1 , a height difference between the first surface and the second surface being in a range of from about 9 nm to about 11 nm.

8 . A field effect transistor (FET), comprising:
an active region surrounded by an isolated region, a sidewall and a first surface of the active region protruding from a second surface of the isolated region; and a metal gate at least covering the sidewall and the first surface of the active region, wherein an Al-containing layer of the metal gate comprises:
a first thickness in proximity to the first surface of the active region; and
a second thickness in proximity to a corner connecting the first surface and the sidewall of the active region, and
a thickness ratio of the second thickness and the first thickness is greater than about 40%.

9 . The FET of claim 8 , wherein the FET is an N-type FET.

10 . The FET of claim 8 , wherein the Al-containing layer comprises TiAl.

11 . The FET of claim 8 , further comprising a TiN layer between the Al-containing layer and the active region.

12 . The FET of claim 8 , wherein the second thickness is in a range of from about 1.5 nm to about 2 nm.

13 . The FET of claim 8 , wherein a length of the metal gate is substantially a length of the first surface, and a width of the metal gate is about 20 nm.

14 . A method for manufacturing a semiconductor structure, comprising:
defining an active region on a semiconductor substrate by forming an isolated region surrounding the active region; forming a work function metal layer over the active region and a portion of the isolated region by an RF sputtering operation; and forming an Al metal layer over the work function metal layer, wherein the forming the work function metal layer comprises tuning an impedance associated with the semiconductor substrate to be greater than an impedance of a grounded wall of a sputtering chamber.

15 . The method of claim 14 , wherein the tuning the impedance associated with the semiconductor substrate comprises tuning a capacitive element, an inductive element, a resistive element, a geometry of the sputtering chamber, or combinations thereof.

16 . The method of claim 14 , wherein the tuning the impedance associated with the semiconductor substrate comprises forming a positive self bias.

17 . The method of claim 14 , wherein the tuning the impedance associated with the semiconductor substrate comprises forming a DC bias of from about 35V to about 60V.

18 . The method of claim 14 , further comprising:
forming a dummy gate over the active region and the isolated region; forming conductive regions in the active region by various implantation operations; and removing the dummy gate by an etching operation.

19 . The method of claim 14 , wherein the defining the active region on a semiconductor substrate comprises a planarization operation to etch back as-deposited dielectric materials.

20 . The method of claim 14 , wherein a ratio of a thinnest portion and a thickest portion of the work function metal layer is controlled to be greater than about 40%.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hung Chi-Cheng
• Wang Yu-Sheng
• Su Ting-Siang
• Su Ching-Hwanq

Classifications

• C23C14/025

  Metallic sublayers · CPC title

• C23C14/185

  by cathodic sputtering · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10P14/44 Primary

  Physical vapour deposition [PVD] · CPC title