Hybrid wafer dicing approach using a polygon scanning-based laser scribing process and plasma etch process

Patent metadata

Field	Value
Publication number	US-2016197015-A1
Application number	US-201514589600-A
Country	US
Kind code	A1
Filing date	Jan 5, 2015
Priority date	Jan 5, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the plurality of integrated circuits. The mask is then patterned with a polygon scanning-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the plurality of integrated circuits.

First claim

1 . A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the plurality of integrated circuits; patterning the mask with a polygon scanning-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits, wherein patterning the mask with the polygon scanning-based laser scribing process comprises scribing at a rate in the range of 10-150 meters/second relative motion speed between laser pulse and the semiconductor wafer surface; and plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of integrated circuits.

2 . The method of claim 1 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises scribing with a laser having a femtosecond pulse width with microjoule level pulse energy, a pulse repetition rate in the range of 5 MHz-1 GHz, and an average power greater than 50 W.

3 . (canceled)

4 . The method of claim 1 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises using a polygon scanner in combination with a telecentric focus unit.

5 . The method of claim 1 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises reflecting a laser beam from a rotating polygon having three or more equal reflecting surfaces.

6 . The method of claim 5 , wherein the rotating polygon has six equal reflecting surfaces.

7 . The method of claim 1 , further comprising:
cleaning the plurality of integrated circuits subsequent to plasma etching the semiconductor wafer.

8 . The method of claim 1 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the plurality of integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.

9 . The method of claim 1 , further comprising:
subsequent to patterning the mask with the polygon scanning-based laser scribing process and prior to plasma etching the semiconductor wafer through the gaps, cleaning the exposed regions of the semiconductor wafer with a plasma process.

10 . A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
laser scribing the semiconductor wafer with a polygon scanning-based laser scribing process to singulate the plurality of integrated circuits, wherein laser scribing the semiconductor wafer with the polygon scanning-based laser scribing process comprises scribing at a rate in the range of 5-150 meters/second relative motion speed between laser pulse and the semiconductor wafer surface; and subsequent to laser scribing the semiconductor wafer, performing a plasma-based cleaning operation to clean sidewalls of the singulated plurality of integrated circuits.

11 . The method of claim 10 , wherein laser scribing the semiconductor wafer with the polygon scanning-based laser scribing process comprises scribing with a laser having a femtosecond pulse width with microjoule level pulse energy, a pulse repetition rate in the range of 5 MHz-1 GHz, and an average power greater than 50 W.

12 . (canceled)

13 . The method of claim 10 , wherein laser scribing the semiconductor wafer with the polygon scanning-based laser scribing process comprises using a polygon scanner in combination with a telecentric focus unit.

14 . The method of claim 10 , wherein laser scribing the semiconductor wafer with the polygon scanning-based laser scribing process comprises reflecting a laser beam from a rotating polygon having three or more equal reflecting surfaces.

15 .- 20 . (canceled)

21 . A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
providing a semiconductor wafer having a mask thereon, the mask comprising a layer covering and protecting the plurality of integrated circuits; patterning the mask with a polygon scanning-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits, wherein patterning the mask with the polygon scanning-based laser scribing process comprises scribing at a rate in the range of 10-150 meters/second relative motion speed between laser pulse and the semiconductor wafer surface; and plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of integrated circuits.

22 . The method of claim 21 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises scribing with a laser having a femtosecond pulse width with microjoule level pulse energy, a pulse repetition rate in the range of 5 MHz-1 GHz, and an average power greater than 50 W.

23 . The method of claim 21 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises using a polygon scanner in combination with a telecentric focus unit.

24 . The method of claim 21 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises reflecting a laser beam from a rotating polygon having three or more equal reflecting surfaces.

25 . The method of claim 24 , wherein the rotating polygon has six equal reflecting surfaces.

26 . The method of claim 21 , further comprising:
cleaning the plurality of integrated circuits subsequent to plasma etching the semiconductor wafer.

27 . The method of claim 21 , wherein patterning the mask with the polygon scanning-based laser scribing process comprises forming trenches in the regions of the semiconductor wafer between the plurality of integrated circuits, and wherein plasma etching the semiconductor wafer comprises extending the trenches to form corresponding trench extensions.

28 . The method of claim 21 , further comprising:
subsequent to patterning the mask with the polygon scanning-based laser scribing process and prior to plasma etching the semiconductor wafer through the gaps, cleaning the exposed regions of the semiconductor wafer with a plasma process.

Assignees

• Lei Wei-Sheng
• Eaton Brad
• Kumar Ajay

Inventors

• Lei Wei-Sheng
• Eaton Brad
• Kumar Ajay

Classifications

• H10P76/2042

  using lasers · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title

• H10P72/0428

  Apparatus for mechanical treatment or grinding or cutting · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title