Device without zero mark layer

US2016190041A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016190041-A1
Application numberUS-201514981873-A
CountryUS
Kind codeA1
Filing dateDec 28, 2015
Priority dateDec 29, 2014
Publication dateJun 30, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

First claim

Opening claim text (preview).

1 . A device comprising: a substrate having first and second surfaces, wherein the substrate is defined with a device region and a frame region surrounding the device region; at least one through silicon via (TSV) opening disposed in the substrate, wherein the TSV opening extends through the first and second surfaces of the substrate and is filled with a conductive material to form TSV contact; an alignment trench disposed in the substrate, wherein the alignment trench extends from the first surface of the substrate into the substrate to a depth shallower than a depth of the TSV contact; a dielectric liner layer disposed over the substrate, wherein the dielectric liner layer is a continuous layer which at least lines a sidewall of the TSV opening, extends over the first surface of the substrate and lines sidewalls of the alignment trench, wherein a top surface of the TSV contact is about coplanar with a top surface of the portion of the continuous dielectric liner layer which extends over the first surface of the substrate; and a redistribution layer (RDL) disposed over the substrate, wherein the RDL comprises TSV contact pad coupled to the TSV contact. 2 . The device of claim 1 wherein the alignment trench includes a width less than about 2 times the thickness of the dielectric liner layer which lines the TSV opening. 3 . The device of claim 2 wherein the alignment trench is completely filled with the same dielectric liner layer which lines the sidewall of the TSV opening and extends over the first surface of the substrate. 4 . The device of claim 2 wherein the alignment trench is lined with the same dielectric liner layer which lines the TSV opening and comprises a closed-off void within the dielectric liner layer in the alignment trench. 5 . The device of claim 2 wherein the alignment trench is lined with the same dielectric liner layer which lines the TSV opening and comprises a void within the dielectric liner layer in the alignment trench which is at least partially filled with the conductive material of the TSV contact. 6 . The device of claim 1 wherein the alignment trench is disposed in the device region of the substrate. 7 . The device of claim 1 wherein the alignment trench is disposed in the frame region of the substrate. 8 . A method for forming a device comprising: providing a substrate having first and second surfaces, wherein the substrate is defined with a device region and a frame region surrounding the device region; forming at least one through silicon via (TSV) opening in the substrate, wherein the TSV opening extends through the first and second surfaces of the substrate; forming an alignment trench corresponding to an alignment mark in the substrate, wherein the alignment trench extends from the first surface of the substrate into the substrate to a depth shallower than a depth of the TSV opening; providing a dielectric liner layer over the substrate, wherein the dielectric liner layer is a continuous layer which at least lines a sidewall of the TSV opening, extends over the first surface of the substrate and lines sidewalls of the alignment trench; providing a conductive layer over the substrate, wherein the conductive layer fills at least the TSV opening to form TSV contact; processing the conductive layer to form the TSV contact such that a top surface of the TSV contact is about coplanar with a top surface of the portion of the continuous dielectric liner layer which extends over the first surface of the substrate; forming a redistribution layer (RDL) over the substrate; and patterning the RDL layer using a reticle to form at least one opening which corresponds to a TSV contact pad, wherein the reticle is aligned using the alignment mark in the substrate. 9 . The method of claim 8 wherein the at least one TSV opening and the alignment trench are formed simultaneously in the substrate. 10 . The method of claim 8 wherein the alignment trench comprises a width less than about 2 times the thickness of the dielectric liner layer which lines the sidewalls of the TSV opening. 11 . The method of claim 10 wherein the dielectric liner layer is provided to simultaneously line the sidewalls of the TSV opening and sidewalls of the alignment trench. 12 . The method of claim 11 wherein the dielectric liner layer completely fills the alignment trench to form the alignment mark. 13 . The method of claim 11 wherein the dielectric liner layer which lines the sidewalls of the alignment trench pinches off to form a closed-off void within the dielectric liner layer in the alignment trench. 14 . The method of claim 13 wherein the dielectric liner layer which lines the sidewalls of the alignment trench and pinches off to form the closed-off void prevents conductive material from being formed therein. 15 . The method of claim 11 wherein the dielectric liner layer which lines the sidewalls of the alignment trench forms a void within the dielectric liner layer in the alignment trench. 16 . The method of 15 wherein the conductive layer which fills at least the TSV opening to form the TSV contact also partially fills the void within the dielectric liner layer in the alignment trench to form the alignment mark. 17 . The method of claim 8 wherein the alignment trench is formed in the device region of the substrate. 18 . The method of claim 8 wherein the alignment trench is formed in the frame region of the substrate. 19 . A method for forming a device comprising: providing a substrate having first and second surfaces, wherein the substrate is defined with a device region and a frame region surrounding the device region; forming at least one through silicon via (TSV) opening and an alignment trench corresponding to an alignment mark in the substrate, wherein the alignment trench extends from the first surface of the substrate into the substrate to a depth shallower than a depth of the TSV opening; providing a dielectric liner layer over the substrate, wherein the dielectric liner layer is a continuous layer which at least lines sidewalls of the TSV opening, extends over the first surface of the substrate and sidewalls of the alignment trench; providing a conductive layer over the substrate, wherein the conductive layer fills at least the TSV opening to form TSV contact; and processing the conductive layer to form the TSV contact such that a top surface of the TSV contact is about coplanar with a top surface of the portion of the continuous dielectric liner layer which extends over the first surface of the substrate. 20 . The method of claim 19 comprising: forming a redistribution layer (RDL) over the substrate, wherein the RDL comprises TSV contact pad coupled to the TSV contact. 21 . The method of claim 19 wherein the dielectric liner layer completely fills the alignment trench to form the alignment mark. 22 . The method of claim 19 wherein the dielectric liner layer which lines the sidewalls of the alignment trench pinches off to form a closed-off void within the dielectric liner layer in the alignment trench. 23 . The method of claim 19 wherein the dielectric liner layer which lines the sidewalls of the alignment trench forms a void within the dielectric liner layer in the alignment trench. 24 . The method of 23 wherein the conductive layer which fills at least the TSV opening to form the TSV contact also partially fills the void within the dielectric liner layer in the a

Assignees

Inventors

Classifications

  • comprising use of blind vias during the manufacture · CPC title

  • for use before dicing · CPC title

  • for alignment · CPC title

  • characterised by the type of information, e.g. logos or symbols · CPC title

  • Adaptable interconnections, e.g. fuses or antifuses · CPC title

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What does patent US2016190041A1 cover?
Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extend…
Who is the assignee on this patent?
Globalfoundries Sg Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/023. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 30 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).