Substrate backside texturing

Patent metadata

Field	Value
Publication number	US-2016141169-A1
Application number	US-201615006965-A
Country	US
Kind code	A1
Filing date	Jan 26, 2016
Priority date	Aug 9, 2013
Publication date	May 19, 2016
Grant date	—

Abstract

Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

First claim

1 . A method, comprising:
determining one or more contact areas on a photolithography tool for the semiconductor substrate; determining a backside surface friction for a semiconductor substrate that is based, at least in part, on:
a frequency of backside features of the semiconductor substrate at one or more portions of the semiconductor substrate, or
an amplitude of the backside features at the one or more portions of the semiconductor substrate; and
processing the semiconductor substrate to obtain a target backside surface friction on the semiconductor substrate, the target backside surface friction comprising backside surface features at a period that is no more than ⅕ of a size of the one or more contact areas.

2 . The method of claim 1 , wherein the contact areas comprise a density of no more than 70 per millimeter.

3 . The method of claim 2 , wherein the amplitude of the backside features varies by no more than 10 nm of each other.

4 . The method of claim 1 , wherein the processing comprises:
applying one or more films to the backside of the semiconductor substrate with at least one chemical agent.

5 . The method of claim 1 , wherein the processing comprises applying a film to the backside of the semiconductor substrate using a vapor deposition process.

6 . The method of claim 5 , wherein the vapor deposition process comprises HMDS.

7 . The method of claim 6 , wherein the processing further comprises changing a surface energy of the semiconductor substrate.

8 . The method of claim 6 , wherein the processing further comprises changing material characteristics or properties of the semiconductor substrate at an atomic level.

9 . A method for improving backside surface friction of a semiconductor substrate, comprising:
determining a type of photolithography tool that will be used to process the semiconductor substrate, the photolithography tool comprising one or more contact areas that will support the semiconductor substrate ; and processing the semiconductor substrate to obtain a backside surface friction that is based, at least in part, on backside features occurring at a period no more than ⅕ of a size of the contact areas.

10 . The method of claim 9 , wherein the the backside surface friction is based, at least in part, on distances between features on the backside of the semiconductor substrate.

11 . The method of claim 9 , wherein the the backside surface friction is based, at least in part, on amplitudes of the features on the backside of the semiconductor substrate.

12 . The method of claim 9 , wherein the backside surface friction comprises a horizontal distance component that is less than a width of the one or more contact areas for at least a portion of the backside of the semiconductor substrate.

13 . The method of claim 9 , wherein the backside surface friction further comprises a vertical distance component that is within 50 nm across at least a portion of the backside of the semiconductor substrate.

14 . A method of reducing lithographic distortion comprising:
treating a backside of a semiconductor substrate; and performing a lithographic process on the semiconductor substrate having the treated backside with a lithographic tool which supports the semiconductor substrate at one or more contact areas, the treating reduces the coefficient of friction between the backside and the one or more contact areas, and the coefficient of friction based, least in part, on the backside comprising features of a period that is no more than ⅕ of a size of the one or more contact areas.

15 . The method of claim 14 , wherein the treating of the backside is based, at least in part, on changing a surface energy of the backside of the semiconductor substrate.

16 . The method of claim 14 , wherein the treating comprises applying a vapor to the backside of the semiconductor substrate.

17 . The method of claim 14 , wherein the treated backside contacts each of the one or more contact areas at a frequency of 5-10 contacts per micron.

18 . The method of claim 14 , wherein the features vary in distance in a direction perpendicular to a surface of the semiconductor substrate by no more than 10 nm.

19 . The method of claim 14 , further comprising:
producing an image on a front surface of the semiconductor substrate; measuring variations in the image from a reference; and producing a modified image on a front surface of a subsequent substrate that varies from the image in accordance with the variations.

Assignees

• Tokyo Electron Ltd

Inventors

• Fonseca Carlos A
• Rathsack Benjamen M
• Smith Jeffrey
• Devilliers Anton J
• Huli Lior

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/76

  using mechanical means, e.g. clamps or pinches · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P90/124 Primary

  by processing the backside of the wafers · CPC title