Dual layer stack for contact formation

Patent metadata

Field	Value
Publication number	US-2016126201-A1
Application number	US-201414532764-A
Country	US
Kind code	A1
Filing date	Nov 4, 2014
Priority date	Nov 4, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.

First claim

1 . A semiconductor device fabrication method comprising:
forming a liner layer upon a dielectric layer; forming an electrically conductive plating layer upon the liner layer; forming an epoxy trench barrier layer upon the plating layer; forming a photoresist layer upon the epoxy trench barrier layer; forming a contact trench within the photoresist layer and the epoxy trench barrier layer wherein the formed contact trench creates photoresist layer portions and epoxy trench barrier layer portions, and wherein the contact trench exposes a portion of the electrically conductive plating layer; plating a contact upon the exposed plating layer within the contact trench, and; subsequent to plating the contact upon the plating layer within the contact trench, removing the photoresist layer portions while maintaining the epoxy trench barrier layer portions.

2 . (canceled)

3 . The semiconductor device fabrication method of claim 2 , further comprising:
subsequent to removing the photoresist layer portions, removing the epoxy trench barrier layer portions to expose the electrically conductive plating layer thereunder.

4 . The semiconductor device fabrication method of claim 2 , further comprising:
removing portions of the electrically conductive plating layer exterior to the contact, such that sidewalls of the electrically conductive plating layer are coplanar with sidewalls the contact.

5 . The semiconductor device fabrication method of claim 2 , further comprising:
removing portions of the liner layer exterior to the contact, such that sidewalls of the liner layer are coplanar with sidewalls the contact.

6 . The semiconductor device fabrication method of claim 2 , wherein the contact is a pillar.

7 . The semiconductor device fabrication method of claim 1 , wherein the contact trench is formed by removing a section of the photoresist layer and removing a section of the epoxy trench barrier layer with a single etchant.

8 . The semiconductor device fabrication method of claim 1 , wherein the photoresist layer and epoxy trench barrier layer have a similar toned photosensitivity.

9 . The semiconductor device fabrication method of claim 1 , wherein the epoxy barrier layer portions protect the electrically conductive plating layer thereunder from corrosion from metal species within a photoresist stripping solution utilized to remove the photoresist layer portions.

10 . A semiconductor device fabrication method comprising:
forming a liner layer upon a dielectric layer; forming an electrically conductive plating layer upon the liner layer; forming an organic material (OM) trench barrier layer upon the plating layer; forming a photoresist layer upon the OM trench barrier layer; forming a contact trench within the photoresist layer and the OM trench barrier layer, wherein the formed contact trench creates photoresist layer portions and OM trench barrier layer portions, and wherein the contact trench exposes a portion of the electrically conductive plating layer; plating a contact upon the exposed plating layer within the contact trench, and; subsequent to plating the contact upon the plating layer within the contact trench, removing the photoresist layer portions while maintaining the OM trench barrier layer portions.

11 . (canceled)

12 . The semiconductor device fabrication method of claim 11 , further comprising:
subsequent to removing the photoresist layer portions, removing the OM trench barrier layer portions to expose the electrically conductive plating layer thereunder.

13 . The semiconductor device fabrication method of claim 11 , further comprising:
removing portions of the electrically conductive plating layer exterior to the contact, such that sidewalls of the electrically conductive plating layer are coplanar with sidewalls the contact.

14 . The semiconductor device fabrication method of claim 11 , further comprising:
removing portions of the liner layer exterior to the contact, such that sidewalls of the liner layer are coplanar with sidewalls the contact.

15 . The semiconductor device fabrication method of claim 11 , wherein the contact is a pillar.

16 . The semiconductor device fabrication method of claim 10 , wherein the contact trench is formed by removing a section of the photoresist layer and removing a section of the OM trench barrier layer with a single etchant.

17 . The semiconductor device fabrication method of claim 10 , wherein the photoresist layer and OM trench barrier layer have a similar toned photosensitivity.

18 . The semiconductor device fabrication method of claim 10 , wherein the OM barrier layer portions protect the electrically conductive plating layer thereunder from corrosion from metal species within a photoresist stripping solution utilized to remove the photoresist layer portions.

19 . The semiconductor device fabrication method of claim 10 , wherein electrically conductive plating layer is copper and wherein the OM barrier layer is an organic solderability preservative that selectively bonds to the conductive plating layer.

20 . (canceled)

Assignees

• IBM

Inventors

• Arvin Charles L
• Cox Harry D
• Erwin Brian M
• Knickerbocker Sarah H
• Mclaughlin Karen P
• Russell David J

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/01971

  Cleaning, e.g. oxide removal · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title