Package-level electromagnetic interference shielding structures for a substrate

Patent metadata

Field	Value
Publication number	US-2016113108-A1
Application number	US-201514919685-A
Country	US
Kind code	A1
Filing date	Oct 21, 2015
Priority date	Oct 21, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A electromagnetic interference shielding device is disclosed having a first substrate one or more surfaces. One or more laminates are operatively attached to the one or more surfaces of the first substrate. A cavity is provided that is defined by the first substrate and its corresponding one or more laminates and at least one inner lateral portion. The cavity is operable to receive one or more microelectromechanical system (MEMS) components. A first conductive structure integrally formed with a trench or via array of the substrate spans a thickness defined by one or more of surfaces of the first substrate, the first conductive structure operable to shield electromagnetic interference between MEMS components assembled with the first substrate.

First claim

What is claimed is:

1 . An electromagnetic interference shielding device, comprising:
a first substrate having one or more surfaces; one or more laminates operatively attached to the one or more surfaces of the first substrate; a cavity defined by the first substrate and corresponding one or more laminates and at least one inner lateral portion, the cavity being operable to receive one or more microelectromechanical system (MEMS) components; and a first conductive structure spanning a thickness defined by one or more of surfaces of the first substrate, the first conductive structure operable to shield electromagnetic interference between MEMS components assembled with the first substrate.

2 . The device of claim 1 , wherein surfaces of the first substrate are operable for die embedding or receiving one or more metallization patterns.

3 . The device of claim 1 , wherein the first conductive structure is integrally formed with a trench of the substrate.

4 . The device of claim 1 , wherein the first conductive structure is integrally formed with a continuous pad of a via array of the substrate, the continuous pad being disposed at a predetermined height relative to the substrate.

5 . The device of claim 3 , wherein the first conductive structure comprises one or more planar surfaces generally orthogonal to the first substrate and extends a predetermined height relative to the substrate.

6 . The device of claim 1 , wherein the cavity is partially or completely filled with conductive or non-conductive material.

7 . The device of claim 5 , wherein the first conductive structure comprises a plurality of individual portions separated and arranged in a predetermined pattern.

8 . The device of claim 5 , wherein one or more planar surfaces of the first conductive structure surround or form a dividing shield between the one or more MEMS components in communication with the first substrate.

9 . The device of claim 5 , wherein the individual portions of the first conductive structure shield the MEMS components from interfering with each other and from interfering with signal lines inside and outside a system-on-package corresponding with the device.

10 . The device of claim 5 , further comprising: a second conductive structure oriented parallel with the substrate and covering the cavity.

11 . The device of claim 10 , wherein the first and second conductive structures are constructed partially or completely from of a conducting magnetic material.

12 . The device of claim 1 , further comprising: the one or more MEMS components electrically connected to the one or more surfaces of the first substrate in a face-down orientation.

13 . The device of claim 12 , wherein the one or more MEMS components are electrically connected to one or more terminals of a system-on-package package corresponding with the device.

14 . The device of claim 12 , further comprising:
a second substrate having one or more surfaces, the second substrate being disposed above of the first substrate; one or more laminates operatively attached to the one or more surfaces of the second substrate; a cavity defined by the second substrate and one or more corresponding laminates and at least one inner lateral portion, the cavity of the second substrate being operable to receive one or more microelectromechanical system (MEMS) components; a first conductive structure spanning a thickness defined by one or more of surfaces of the second substrate and extending outward from the second substrate a predetermined distance, the first conductive structure being integrally formed with a trench of the second substrate and operable to shield electromagnetic interference between MEMS components assembled with the second substrate.

15 . The device of claim 5 , wherein the first conductive structure is constructed from a multi-layer structure comprising: a magnetic layer positioned between a non-magnetic layer and an insulator layer.

16 . The device of claim 15 , wherein each of the multi-layer structure is constructed from the same metal.

17 . An electromagnetic interference trench-based shielding system, comprising:
a substrate having one or more surfaces, the substrate being operable to receive one or more microelectromechanical system (MEMS) components; one or more laminates operatively attached to the one or more surfaces of the first substrate; a first conductive structure spanning a thickness defined by one or more of surfaces of the substrate, the first conductive structure in communication with a trench of the substrate and oriented generally orthogonal to the first substrate; wherein the first conductive structure separates at least two MEMS components assembled to the substrate.

18 . The system of claim 18 , wherein the first conductive structure is integrally formed with the trench and extends a predetermined height away from the substrate.

19 . A process of fabricating one or more electromagnetic shields between components for ultra-thin radiofrequency packages, the process comprising:
selectively inserting one or more through package vias (TPVs) in a substrate; removing residue from an edge of the one or more TPVs by desmearing; electroless seed plating the substrate thereby increasing thickness and conductivity; coating the substrate by electrolytic plating with a metal; thinning upper and lower surfaces of the substrate; laminating upper and lower surfaces of the substrate with a first layer of photoresist film; exposing the first layer of photoresist film of the upper and lower surfaces to wavelengths in the ultraviolet spectrum; subtractive etching the electrolytic plating on the upper and lower surfaces of the substrate and stripping the photoresist film; electroless seed layer plating on the upper and lower surfaces of the substrate; applying a relatively a second layer of photoresist film to the upper surface of the substrate, the second layer being thicker than the first layer of photoresist film; exposing the second layer of photoresist film to wavelengths in the ultraviolet spectrum; electroplating the second layer of photoresist film with a metal; stripping the relatively thick photoresist film and etching the electroless seed layer on the upper surface of the substrate thereby forming one or more electromagnetic interference (EMI) shields in communication with corresponding trenches of the substrate; and laminating one or more layers to apply uniform pressure to uneven profiles of the substrate caused by the one or more EMI shields.

20 . The method of claim 19 , wherein the TPVs are selectively inserted using laser ablation and the substrate is electroless seed plated with copper.

Assignees

• Georgia Tech Res Inst

Inventors

• Sundaram Venkatesh
• Kim Sung-Jin
• Liu Fuhan
• Sitaraman Srikrishna
• Tummala Rao R

Classifications

• H05K1/183

  associated with components mounted in and supported by recessed areas of the PCBs · CPC title

• H05K3/022

  Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates · CPC title

• H05K2201/09481

  Via in pad; Pad over filled via · CPC title

• H05K2201/032

  Materials · CPC title

• H05K2201/10537

  Attached components · CPC title