Insulated Gate Bipolar Transistor Comprising Negative Temperature Coefficient Thermistor

Patent metadata

Field	Value
Publication number	US-2016111415-A1
Application number	US-201514880924-A
Country	US
Kind code	A1
Filing date	Oct 12, 2015
Priority date	Oct 21, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

First claim

1 . An insulated gate bipolar transistor, comprising:
an emitter terminal at a first surface of a semiconductor body; a collector terminal at a second surface of the semiconductor body; a first zone of a first conductivity type in the semiconductor body between the first and second surfaces; a collector injection structure adjoining the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other; and further comprising a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

2 . The insulated gate bipolar transistor of claim 1 , wherein a short region of the first zone is sandwiched between the first and second parts along a lateral direction.

3 . The insulated gate bipolar transistor of claim 2 , wherein the first zone includes a drift region having a smaller doping concentration than the short region.

4 . The insulated gate bipolar transistor of claim 3 , further comprising a doped region adjoining the second surface in a junction termination area surrounding a transistor cell area including the first and second parts, wherein a doping concentration in the doped region differs from the doping concentration of the drift region.

5 . The insulated gate bipolar transistor of claim 4 , wherein the doped region is of the second conductivity type having a smaller doping concentration than the first and second parts.

6 . The insulated gate bipolar transistor of claim 4 , wherein the doped region is of the first conductivity type having a same profile of doping concentration along a vertical direction as the area between the first and second parts.

7 . The insulated gate bipolar transistor of claim 1 , wherein the negative temperature coefficient thermistor is sandwiched between the first and second parts along a lateral direction.

8 . The insulated gate bipolar transistor of claim 1 , wherein an interface between the negative temperature coefficient thermistor and a first part of the first zone is sandwiched between the first and second parts along a lateral direction.

9 . The insulated gate bipolar transistor of claim 1 , wherein the negative temperature coefficient thermistor is arranged between a first part of the first zone and a collector contact electrically connected to the collector injection structure.

10 . The insulated gate bipolar transistor of claim 1 , wherein the first lateral distance between the first and second parts is in a range between 0.5 μm and 500 μm.

11 . The insulated gate bipolar transistor of claim 1 , wherein the collector injection structure further comprises a third part and a fourth part at a second lateral distance from each other; and a second part of the first zone sandwiched between the third and fourth parts along the lateral direction is in contact to a collector contact electrically connected to the collector injection structure.

12 . The insulated gate bipolar transistor of claim 1 , wherein the first and second parts are arranged in a transistor cell area.

13 . The insulated gate bipolar transistor of claim 1 , wherein a lateral dimension of the first part is greater than a lateral dimension of the second part.

14 . The insulated gate bipolar transistor of claim 1 , wherein the negative temperature coefficient thermistor is a material characterized by a phase change from an amorphous phase into a crystalline phase at a critical temperature.

15 . The insulated gate bipolar transistor of claim 14 , wherein the material is a chalcogenide.

16 . The insulated gate bipolar transistor of claim 15 , wherein the chalcogenide includes at least one of GeTe and Ge 2 Sb 2 Te 5 .

17 . The insulated gate bipolar transistor of claim 1 , wherein the negative temperature coefficient thermistor is a semiconductor material having a bandgap smaller than a bandgap of a semiconductor material of the semiconductor body.

18 . A method of manufacturing an insulated gate bipolar transistor, comprising:
forming a collector injection structure at a second surface of a semiconductor body having opposite first and second surfaces, wherein the semiconductor body includes a first zone of a first conductivity and the collector injection structure is of a second conductivity type comprising a first part and a second part at a first lateral distance from each other; and forming a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

19 . The method of claim 18 , wherein the collector injection structure and the negative temperature coefficient thermistor are formed by
etching a trench into the semiconductor body from the second surface, wherein the trench separates the first and second parts; and forming the negative temperature coefficient thermistor in the trench.

20 . The method of claim 18 , wherein the first part and the second part are formed by introducing dopants into the semiconductor body from the second surface through a patterned mask.

Assignees

• Infineon Technologies Austria
• Infineon Technologies Ag

Inventors

• Basler Thomas
• Griebl Erich
• Mahler Joachim
• Pedone Daniel
• Scholz Wolfgang
• Seng Philipp
• Tuerkes Peter
• Voss Stephan

Classifications

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D12/441

  Vertical IGBTs · CPC title