Methods for singulating semiconductor wafer

Patent metadata

Field	Value
Publication number	US-2016104626-A1
Application number	US-201514881181-A
Country	US
Kind code	A1
Filing date	Oct 13, 2015
Priority date	Oct 13, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

First claim

What is claimed is:

1 . A method for dicing a wafer comprising:
providing a wafer having first and second major surfaces, wherein the wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer; providing a film over first or second major surface of the wafer, wherein the film covers at least areas corresponding to the main device regions; and using the film as an etch mask, plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

2 . The method of claim 1 wherein the first major surface of the wafer is an active surface where integrated circuits are defined and the second major surface of the wafer is a passive surface.

3 . The method of claim 2 wherein the wafer is processed to include a passivation layer formed over at least main device regions on the active surface of the wafer.

4 . The method of claim 3 comprising providing a support platform and attaching the active surface of the wafer to the support platform.

5 . The method of claim 4 wherein the passivation layer does not extend over the dicing channels.

6 . The method of claim 5 wherein the wafer comprises one or more monitoring patterns formed in the dicing channels of the wafer and the one or more monitoring patterns contact the support platform when the active surface of the wafer is attached to the support platform.

7 . The method of claim 6 wherein providing the film comprises providing a backside protective layer over the passive surface of the wafer.

8 . The method of claim 7 wherein providing the film further comprises processing the backside protective layer by selectively removing portions of the backside protective layer disposed over areas corresponding to the dicing channels/streets on the active surface of the wafer, wherein the processed backside protective layer serves as the etch mask and the plasma etching process removes the exposed semiconductor material of the wafer through the passive surface of the wafer.

9 . The method of claim 8 comprising removing the individual dies from the support platform, wherein the monitoring patterns remain on surface of the support platform after the individual dies are removed.

10 . The method of claim 3 wherein the wafer comprises one or more monitoring patterns formed in the dicing channels of the wafer.

11 . The method of claim 10 wherein the passivation layer covers the main device regions and extends to the dicing channels covering the one or more monitoring patterns on the active surface of the wafer.

12 . The method of claim 11 wherein providing the film comprises providing a backside protective layer over the passive surface of the wafer.

13 . The method of claim 12 wherein providing the film further comprises processing the backside protective layer by selectively removing portions of the backside protective layer disposed over areas corresponding to the dicing channels/streets on the active surface of the wafer, wherein the processed backside protective layer serves as the etch mask and the plasma etching process removes the exposed semiconductor material of the wafer through the passive surface of the wafer.

14 . The method of claim 12 comprising removing the individual dies from the support platform using a die pick up process, wherein the passivation layer of each die is severed and separated from each other when the dies are removed by the die pick up process.

15 . The method of claim 12 comprising performing a non-etching process through the gaps formed during the plasma etching process to severe and separate the passivation layer of each die from each other.

16 . The method of claim 15 wherein performing the non-etching process comprises applying a jet of air blow or laser beam through the gaps.

17 . The method of claim 2 wherein providing the film comprising providing a passivation layer over the active surface of the wafer, wherein the passivation layer is formed over main device regions and dicing channels on the active surface of the wafer.

18 . The method of claim 17 wherein providing the film further comprises processing the passivation layer by selectively removing portions of the passivation layer disposed over the dicing channels/streets on the active surface of the wafer, wherein the processed passivation layer serves as the etch mask and the plasma etching process removes the exposed semiconductor material of the wafer through the active surface of the wafer.

19 . The method of claim 2 wherein providing the film comprises providing a die attach film over the passive surface of the wafer.

20 . The method of claim 19 wherein providing the film further comprises processing the die attach film by selectively removing portions of the die attach film disposed over areas corresponding to the dicing channels/streets on the active surface of the wafer, wherein the processed die attach film serves as the etch mask and the plasma etching process removes the exposed semiconductor material of the wafer through the passive surface of the wafer.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Nelson William John
• Suthiwongsunthorn Nathapong
• Ho Beng Yeung
• Ong Poh Leng Wilson

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/301

  for alignment · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title