System, method and computer-accessible medium for providing secure split manufacturing

Patent metadata

Field	Value
Publication number	US-2016034628-A1
Application number	US-201414775164-A
Country	US
Kind code	A1
Filing date	Mar 14, 2014
Priority date	Mar 14, 2013
Publication date	Feb 4, 2016
Grant date	—

Abstract

Exemplary systems, methods and computer-accessible mediums can secure split manufacturing of an integrated circuit by modifying a previous location of at least one pin to a further location of the at least one pin based on a fault analysis procedure. A determination of the further location can include an iterative procedure that can be a greedy iterative procedure. The modification of the location of the at least one partition pin can be performed by swapping at least one further partition pin with the at least one partition pin.

First claim

What is claimed is:

1 . A non-transitory computer-accessible medium having stored thereon computer-executable instructions for providing or securing split manufacturing of an integrated circuit (“IC”), wherein, when a computer hardware arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
modifying a previous location of at least one partition pin to a further location of the at least one partition pin based on a fault analysis procedure.

2 . The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the further location using an iterative procedure.

3 . The computer-accessible medium of claim 2 , wherein the iterative procedure comprises a greedy iterative procedure.

4 . The computer-accessible medium of claim 1 , wherein the modification procedure is performed by swapping at least one further partition pin with the at least one partition pin.

5 . The computer-accessible medium of claim 4 , wherein the computer arrangement is further configured to determine the further location based on an effect of swapping the at least one partition pin and the at least one further partition pin on a maximum number of outputs of the IC.

6 . The computer-accessible medium of claim 4 , wherein the computer arrangement is further configured to determine at least one further pair of pins to swap based on an effect of the swapping as a function of a maximum number of outputs.

7 . The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the further location based, at least in part, on a Hamming Distance.

8 . The computer-accessible medium of claim 7 , wherein the Hamming Distance is approximately 50%.

9 . The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the further location based, at least in part, on an Avalanche Criterion.

10 . The computer-accessible medium of claim 1 , wherein the at least one partition pin and at least one further partition pin are interconnected based on at least one Front End Of Line (FEOL) metal layer, wherein connections inside at least one partition are made on at least one Back End Of Line (BEOL) metal layer, and wherein the at least one FEOL and at least one BEOL layers are manufactured separately.

11 . The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine the further location using a netlist.

12 . The computer-accessible medium of claim 12 , wherein the computer arrangement is further configured to identify the further location in the netlist using a cumulative sum of corrupted output bits over a set of random test patterns.

13 . The computer-accessible medium of claim 1 , wherein the computer processing arrangement is further configured to deceive an attacker into making at least one wrong connection between the modified at least one partition pin based on a reverse engineered BEOL netlist with missing FEOL connections.

14 . A method providing or securing split manufacturing of an integrated circuit (“IC”), comprising:
using a computer hardware arrangement, modifying a previous location of at least one pin to a further location of the at least one pin based on a fault analysis procedure.

15 . The method of claim 14 , further comprising determining the further location using an iterative procedure.

16 . The method of claim 15 , wherein the iterative procedure comprises a greedy iterative procedure.

17 . The method of claim 14 , wherein the modification procedure is performed by swapping at least one further partition pin with the at least one partition pin.

18 . The method of claim 1 , wherein the further location is determined based, at least in part, on at least one of a Hamming Distance or an Avalanche Criterion.

19 . The method of claim 18 , wherein the Hamming Distance is approximately 50%.

20 . An integrated circuit, comprising:
at least one pin whose location has been modified based on a fault analysis procedure.

Assignees

• Univ New York

Inventors

• Rajendran Jeyavijayan
• Sinanoglu Ozgur
• Karri Ramesh

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title

• G06F17/5072 Primary

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic