Multi-via interconnect structure and method of manufacture

Patent metadata

Field	Value
Publication number	US-2015228584-A1
Application number	US-201414257759-A
Country	US
Kind code	A1
Filing date	Apr 21, 2014
Priority date	Feb 13, 2014
Publication date	Aug 13, 2015
Grant date	—

Abstract

An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.

First claim

What is claimed is:

1 . An apparatus comprising:
a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first metal lines formed in the first dielectric layers over the first substrate, wherein the first substrate has a thickness less than about 5 μm; a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second metal lines formed in the second dielectric layers over the second substrate; and a plurality of multi-via interconnect structures, a first multi-via interconnect structure extending from a second surface of the first semiconductor chip to a first one of the plurality of first metal lines in the first semiconductor chip and to a second one of the plurality of second metal lines in the second semiconductor chip.

2 . The apparatus of claim 1 , wherein the first multi-via interconnect structure of the plurality of multi-via interconnect structures is electrically coupled to a first voltage source and a second multi-via interconnect structure of the plurality of multi-via interconnect structures is electrically coupled to a second voltage source, the first voltage source being different than the second voltage source.

3 . The apparatus of claim 2 , wherein the first voltage source provides a first voltage value, the second voltage source provides a second voltage value, the first voltage value being different than the second voltage value.

4 . The apparatus of claim 1 , wherein the first semiconductor chip is a first technology node chip and the second semiconductor chip is a second technology node chip, the first technology node chip being a different technology node than the second technology node chip.

5 . The apparatus of claim 1 , wherein a pitch of the plurality of multi-via interconnect structures is less than or equal to about 10 μm.

6 . The apparatus of claim 1 , wherein a pitch of the plurality of multi-via interconnect structures is less than or equal to about 5 μm.

7 . The apparatus of claim 1 , wherein a pitch of the plurality of multi-via interconnect structures is less than or equal to about 1 μm.

8 . The apparatus of claim 1 , wherein the first semiconductor chip is a first functional type and the second semiconductor chip is a second functional type, the first functional type being different than the second functional type.

9 . The apparatus of claim 1 , wherein a substrate of the first semiconductor chip has a thickness less than about 3 μm.

10 . The apparatus of claim 1 , wherein the first one of the first metal lines is not electrically connected to electrical circuitry on the first semiconductor chip.

11 . The apparatus of claim 1 , wherein the multi-via interconnect structure provides an electrical connection between electrical circuitry on the first semiconductor chip and electrical circuitry on the second semiconductor chip, the multi-via interconnect structure not providing an external electrical connection to the electrical circuitry on the first semiconductor chip and the electrical circuitry on the second semiconductor chip.

12 . An apparatus comprising:
a first semiconductor chip comprising a first substrate, a plurality of first dielectric layers and a plurality of first features formed in the first dielectric layers over the first substrate, the first semiconductor chip being a first technology node; a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second dielectric layers and a plurality of second features formed in the second dielectric layers over the second substrate, the second semiconductor chip being a second technology node, the first technology node being different than the second technology node; and a plurality of multi-via interconnect structures, each of the multi-via interconnect structures extending from a second surface of the first semiconductor chip to one or more of the plurality of first features in the first semiconductor chip and to one or more of the plurality of second features in the second semiconductor chip.

13 . The apparatus of claim 12 , wherein a first multi-via interconnect structure of the plurality of multi-via interconnect structures is electrically coupled to a first voltage source and a second multi-via interconnect structure of the plurality of multi-via interconnect structures is electrically coupled to a second voltage source, the first voltage source being different than the second voltage source, the first voltage source provides a first voltage value, the second voltage source provides a second voltage value, the first voltage value being different than the second voltage value.

14 . The apparatus of claim 12 , wherein a pitch of the plurality of multi-via interconnect structures is less than or equal to about 5 μm.

15 . A method comprising:
providing a bonded structure having a first semiconductor chip having a first substrate bonded to a second semiconductor chip having a second substrate, the first substrate having one or more overlying first dielectric layers and a first pad in the one or more first dielectric layers, the second substrate having one or more overlying second dielectric layers and a second pad in the one or more second dielectric layers, the first substrate being bonded to the second substrate such that the first dielectric layers face the second dielectric layers, wherein the first semiconductor chip is a first technology node chip and the second semiconductor chip is a second technology node chip, the first technology node chip being a different technology node than the second technology node chip; forming a first opening extending through the first substrate; forming a second opening extending from the first opening to the first pad; and forming a third opening extending from the first pad to the second pad; and forming a first multi-via interconnect structure in the first opening, second opening, and the third opening.

16 . The method of claim 15 , further comprising forming a second multi-via interconnect structure, wherein the first multi-via interconnect structure is electrically coupled to a first voltage source and the second multi-via interconnect structure is electrically coupled to a second voltage source, the first voltage source being different than the second voltage source, wherein the first voltage source provides a first voltage value, the second voltage source provides a second voltage value, the first voltage value being different than the second voltage value.

17 . The method of claim 15 , further comprising forming a second multi-via interconnect structure.

18 . The method of claim 17 , wherein a pitch of the first and second multi-via interconnect structures is less than or equal to about 10 μm.

19 . The method of claim 17 , wherein a pitch of the first and second multi-via interconnect structures is less than or equal to about 5 μm.

20 . The method of claim 17 , wherein a pitch of the first and second multi-via interconnect structures is less than or equal to about 1 μm.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Huang Yu-Fei
• Li Ming Xiang
• Wan Edward
• Chen Jacob
• Yaung Dun-Nian
• Chen Cheng-Eng Daniel

Classifications

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title