Method for Singulating Packaged Integrated Circuits and Resulting Structures

Patent metadata

Field	Value
Publication number	US-2015118797-A1
Application number	US-201314067644-A
Country	US
Kind code	A1
Filing date	Oct 30, 2013
Priority date	Oct 30, 2013
Publication date	Apr 30, 2015
Grant date	—

Abstract

A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure.

First claim

What is claimed is:

1 . A method of packaging an integrated circuit comprising:
forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region; covering the first and second integrated circuits with a molding compound; sawing through a top portion of the molding compound while leaving a bottom portion of the molding compound remaining, using a first saw blade having a first thickness; and sawing through the bottom portion of the molding and the wafer using a second saw blade having a second thickness that is less than the first thickness.

2 . The method of claim 1 , wherein the step of sawing through the a top portion of the molding compound while leaving a bottom portion of the molding compound remaining comprises leaving about 15 microns to about 35 microns of molding compound remaining.

3 . The method of claim 1 , wherein the first thickness is about 40 microns to about 200 microns, and the second thickness is about 15 microns to about 25 microns.

4 . The method of claim 1 , wherein covering the first and second integrated circuits with a molding compound comprises:
depositing a liquid molding compound over the first and second integrated circuits; and curing the liquid molding compound.

5 . The method of claim 1 , wherein covering the first and second integrated circuits with a molding compound comprises forming the molding compound to thickness of from about 80 microns to about 120 microns.

6 . The method of claim 1 , further comprising applying dicing tape to a bottom surface of the wafer.

7 . The method of claim 6 wherein a portion of the dicing tape remains between the first integrated circuit and the second integrated circuit after the step of sawing through the bottom portion of the molding and the wafer.

8 . The method of claim 1 , wherein the first thickness is about 200 microns, and the second thickness is about 42.

9 . A method of packaging an integrated circuit comprising:
forming a first integrated circuit on a wafer and a second integrated on the wafer, the first integrated circuit and second integrated circuit being separated by a singulation region; applying dicing tape to a side of the wafer opposite to the side on which the first integrated circuit and second integrated circuit are formed; forming on a first major surface of the first integrated circuit a first electrical contact pad and forming on a second major surface of the second integrated circuit a second electrical contact pad; forming a first connector on the first contact pad and a second connector on the second contact pad; covering the first major surface and the second major surface with a molding compound, the molding compound extending over the singulation region; aligning the wafer to a saw blade so that the saw blade is aligned to the singulation region; sawing through a top portion of the molding compound with a saw blade having a first width, wherein a bottom portion of the molding compound remains in the singulation region after the sawing step; and singulating the first integrated circuit and the second integrated circuit by sawing through the bottom portion of the molding compound and through the wafer with a second saw blade, the second saw blade having a second width that is less than the first width, wherein at least a portion of the dicing tape remains in the singulation region after the singulating step.

10 . The method of claim 9 , wherein the bottom portion of the molding compound is at least 25 microns in thickness.

11 . The method of claim 9 , wherein the first width is at least five times greater than the second width.

12 . The method of claim 9 , wherein the first width is about 200 microns and the second width is about 30 microns.

13 . The method of claim 9 , wherein the first connector is selected from the group consisting of a solder ball, a solder bump, and a copper pillar.

14 . The method of claim 9 , wherein the first width is about 200 microns and the second width is about 42 microns.

15 . The method of claim 9 , wherein the molding compound has a thickness of from about 100 microns to about 140 microns.

16 . A method of packaging an integrated circuit comprising:
providing a wafer having formed thereon a plurality of integrated circuits and a plurality of scribe lines separating adjacent integrated circuits, each integrated circuit including at least one contact pad formed on a top major surface thereof; electrically connecting to the respective contact pads respective connectors; forming a liquid molding compound over the wafer, the liquid molding compound cover the top major surface of the respective integrated circuits and the plurality of scribe lines; curing the liquid molding compound to solidify it; aligning with a first scribe line, a first saw blade having a first thickness; sawing through a top portion of the cured molding compound while leaving a bottom portion of the cured molding compound remaining, thus forming a kerf in the top portion of the cured molding compound; aligning a second saw blade to the kerf; and sawing through the bottom portion of the cured molding compound and the wafer using the second saw blade, the second saw blade having a second thickness different from the first thickness.

17 . The method of claim 16 , wherein the first thickness is about 40 to about 200 microns and the second thickness is about 15 to about 25 microns.

18 . The method of claim 16 , wherein the bottom portion of the cured molding compound has a thickness of from about 15 microns to about 35 microns.

19 . The method of claim 16 , wherein electrically connecting to the respective contact pads respective connectors comprises:
forming a passivation layer over the contact pads; forming a patterned redistribution layer over the passivation layer, portions of the patterned redistribution layer being in electrical contact with respective ones of the contact pads; and forming respective solder balls on respective portions of the patterned redistribution layer.

20 . The method of claim 19 , wherein the solder balls are formed directly on and in physical contact with the patterned redistribution layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liu Ming-Kai
• Wang Yen-Ping
• Wu Kai-Chiang

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/014 Primary

  using batch processing · CPC title

• H10W74/016 Primary

  using moulds · CPC title