Self aligned interconnect structures

Patent metadata

Field	Value
Publication number	US-10199264-B2
Application number	US-201815875212-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Nov 29, 2016
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.

First claim

What is claimed:

1. A method comprising:
forming a first metallization structure composed of a Pt group material;
recessing the first metallization structure;
forming a second of metallization structure of the Pt group material on the first metallization structure; and
forming a trench at the first metallization structure such that the first metallization structure and the second metallization structure are self-aligned,
wherein the trench is formed by an overetching of a non-recessed portion of the first metallization structure.

2. The method of claim 1 , wherein the forming of the first metallization structure and the second metallization structure are provided by a substantive etching process.

3. The method of claim 1 , wherein the trench is formed into an airgap by deposition of insulator material.

4. The method of claim 1 , wherein the Pt group material is Ru.

5. The method of claim 4 , further comprising annealing the Ru of the first metallization structure.

6. A method comprising:
forming an interconnect structure composed of a lower wiring layer and an interconnect portion extending from the lower wiring layer, the interconnect portion being self-aligned and in direct contact with an upper level via metallization,
forming an airgap in dielectric material above the lower wiring layer and adjacent to the interconnect portion,
wherein the interconnect structure including the lower wiring layer and the interconnect portion as well as the upper level via metallization are composed of a Pt group material.

7. The method of claim 6 , wherein the interconnect structure and the upper level via metallization are devoid of a dielectric capping material at an interface.

8. The method of claim 6 , wherein the interconnect structure is composed of Ru.

9. The method of claim 6 , wherein the interconnect structure is composed of one of Ru, Rh, Pt, Ir, Os and Pd.

10. The method of claim 6 , further comprising annealing the Pt group material.

11. The method of claim 6 , wherein the interconnect structure and the upper level via metallization are of a same metallization.

12. The method of claim 6 , wherein the interconnect structure and the upper level via metallization are in direct physical and electrical contact with one another, devoid of a capping material.

13. A method comprising:
forming a metallization feature at a first level composed of a Pt group material;
forming an interconnect structure which is formed from the metallization feature and is composed of the Pt group material;
forming an airgap provided in dielectric material, directly adjacent to the interconnect structure; and
forming an upper level via metallization in direct electrical and physical contact with the interconnect structure and which is composed of the Pt group material and which is self-aligned with the interconnect structure below.

14. The method of claim 13 , wherein the airgap is formed below the upper level via metallization.

15. The method of claim 14 , wherein the interconnect structure and the upper level via metallization are devoid of a dielectric capping material at an interface.

16. The method of claim 14 , wherein the Pt group material is Ru.

17. The method of claim 16 , wherein the Pt group material is an annealed metal.

18. The method of claim 14 , wherein the Pt group material is one of Ru, Rh, Pt, Ir, Os and Pd.

Assignees

• Globalfoundries Inc

Inventors

• Zhang Xunyuan
• Augur Roderick A
• Kim Hoon

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/4432

  the principal metal being a noble metal, e.g. gold · CPC title

• H10W20/432

  comprising crossing interconnections · CPC title