Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12598933-B2
Application number	US-202318241773-A
Country	US
Kind code	B2
Filing date	Sep 1, 2023
Priority date	Sep 1, 2023
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.

First claim

What is claimed is:

1 . A method, comprising:
providing a semiconductor substrate; forming a fin protruding from the semiconductor substrate; forming a silicon-containing layer over the fin; and patterning the silicon-containing layer to form a gate structure over the fin, wherein patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.

2 . The method of claim 1 , wherein the silicon-containing gas includes a halogen and the nitrogen-containing gas includes N 2 .

3 . The method of claim 1 , wherein the passivant is free of any oxygen-containing gas.

4 . The method of claim 1 , further comprising forming a patterned mask over the silicon-containing layer such that patterning the silicon-containing layer removes portions of the silicon-containing layer exposed by the patterned mask.

5 . The method of claim 1 , wherein patterning the silicon-containing layer causes the passivant to react with the silicon-containing layer to form a passivation layer that includes at least one silicon nitride (SiN)-containing material.

6 . The method of claim 5 , wherein the passivation layer includes Si x NBr y and one of Si x NCl y or Si x NF y , x and y being greater than 0.

7 . The method of claim 5 , wherein a portion of the passivation layer is formed to have a thickness that decreases along a sidewall of the gate structure towards the semiconductor substrate.

8 . The method of claim 5 , wherein a portion of the passivation layer is formed to have a domed profile over a top surface of the gate structure.

9 . A method, comprising:
providing a semiconductor substrate; forming a fin protruding from the semiconductor substrate; depositing a silicon layer over the fin; and etching the silicon layer to form a gate structure using an etchant and a passivant, wherein etching the silicon layer forms a silicon-nitride-containing passivation layer over a top portion of a sidewall of the gate structure, wherein the silicon-nitride-containing passivation layer includes at least one halogen-containing silicon nitride.

10 . The method of claim 9 , further comprising:
forming a patterned mask over the silicon layer before etching the silicon layer; and removing the silicon-nitride-containing passivation layer after etching the silicon layer.

11 . The method of claim 9 , wherein etching the silicon layer includes depositing the passivant using a chemical vapor deposition (CVD) process.

12 . The method of claim 9 , wherein a bottom portion of the sidewall of the gate structure is free of the silicon-nitride-containing passivation layer.

13 . The method of claim 9 , wherein a composition of the passivant is free of oxygen.

14 . The method of claim 9 , wherein the etchant includes Cl 2 , HBr, or a combination thereof.

15 . The method of claim 14 , wherein the etchant reacts with the silicon layer to form a product having a same composition as the passivant.

16 . A method, comprising:
providing a semiconductor substrate; forming a fin protruding from the semiconductor substrate; depositing a silicon layer over the fin; forming a patterned mask over the silicon layer; and etching portions of the silicon layer exposed by the patterned mask to form a gate structure, wherein etching the portions of the silicon layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas, resulting in a silicon-nitride-containing passivation layer over a sidewall of the gate structure.

17 . The method of claim 16 , wherein the passivant includes N 2 and a silicon-and-halogen-containing gas, the passivant being free of any oxygen-containing gas.

18 . The method of claim 16 , wherein the silicon-containing gas includes a halogen and the nitrogen-containing gas includes N 2 .

19 . The method of claim 16 , wherein the silicon-nitride-containing passivation layer is formed to have a thickness that decreases along the sidewall of the gate structure below the patterned mask.

20 . The method of claim 19 , wherein a bottommost portion of the sidewall of the gate structure is free of the silicon-nitride-containing passivation layer.

Assignees

• Tokyo Electron Ltd

Inventors

• Marion Jason
• Kaiser Alexander
• Yoshida Yusuke
• Han Yun

Classifications

• H10P14/6316

  Formation by nitridation, e.g. nitridation of the substrate · CPC title

• H10P14/416 Primary

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10P50/283

  by chemical means · CPC title