Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12598748-B2
Application number	US-202217983570-A
Country	US
Kind code	B2
Filing date	Nov 9, 2022
Priority date	Sep 15, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

First claim

What is claimed is:

1 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a first dielectric layer, a first polysilicon layer, and a second polysilicon layer on a substrate; forming a second dielectric layer and a third polysilicon layer on the second polysilicon layer; forming a dielectric stack comprising interleaved third dielectric layers and fourth dielectric layers on the third polysilicon layer; forming a channel hole penetrating the dielectric stack, the third polysilicon layer, the second dielectric layer, the second polysilicon layer, the first polysilicon layer, and the first dielectric layer to expose the substrate; performing an oxidation operation to form a fifth dielectric layer on the first polysilicon layer and the second polysilicon layer exposed by sidewalls of the channel hole; forming a channel structure in the channel hole; removing the substrate, the first polysilicon layer, the second polysilicon layer, the second dielectric layer, and a bottom portion of the channel structure; and forming a fourth polysilicon layer over the channel structure.

2 . The method of claim 1 , wherein forming the first dielectric layer, the first polysilicon layer, and the second polysilicon layer on the substrate, comprises:
forming the first dielectric layer on the substrate; forming an undoped polysilicon layer or a carbon-doping polysilicon layer on the first dielectric layer as the first polysilicon layer; and forming a p-type doping polysilicon layer on the undoped polysilicon layer or the carbon-doping polysilicon layer as the second polysilicon layer, wherein the first polysilicon layer and the second polysilicon layer are formed in a same deposition operation.

3 . The method of claim 1 , further comprising:
performing an ammonia (NH 3 ) treatment on the second polysilicon layer.

4 . The method of claim 1 , wherein forming the second dielectric layer and the third polysilicon layer on the second polysilicon layer, comprises:
forming the second dielectric layer on the second polysilicon layer; and forming an undoped polysilicon layer on the second dielectric layer.

5 . The method of claim 1 , further comprising:
performing an NH 3 treatment on the third polysilicon layer.

6 . The method of claim 1 , wherein performing the oxidation operation to form the fifth dielectric layer on the first polysilicon layer and the second polysilicon layer exposed by the sidewalls of the channel hole, comprises:
performing a wet oxidation operation on the sidewalls of the channel hole.

7 . The method of claim 1 , wherein performing the oxidation operation to form the fifth dielectric layer on the first polysilicon layer and the second polysilicon layer exposed by the sidewalls of the channel hole, comprises:
forming the fifth dielectric layer on the first polysilicon layer and the second polysilicon layer exposed by the sidewalls of the channel hole; and forming a sixth dielectric layer on the third polysilicon layer exposed by the sidewalls of the channel hole.

8 . The method of claim 7 , wherein a first oxidation rate of the oxidation operation on the first polysilicon layer is lower than a second oxidation rate of the oxidation operation on the second polysilicon layer.

9 . The method of claim 7 , wherein a third oxidation rate of the oxidation operation on the third polysilicon layer is lower than the second oxidation rate of the oxidation operation on the second polysilicon layer.

10 . The method of claim 1 , wherein, after performing the oxidation operation, the channel hole comprises a first width at a location of the dielectric stack and a second width at a location of the second polysilicon layer, and the first width is larger than the second width.

11 . The method of claim 10 , wherein the second width is less than 40 nanometers.

12 . The method of claim 1 , wherein forming the channel structure in the channel hole, comprises:
forming a memory film over the sidewalls of the channel hole; and forming a semiconductor channel over the memory film above the second polysilicon layer.

13 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure comprising at least a polysilicon layer and a dielectric stack on a substrate; forming a channel hole penetrating the stack structure; performing an oxidation operation on sidewalls of the channel hole to form a dielectric layer on the polysilicon layer exposed by the channel hole, wherein a first width of the channel hole at a location of the dielectric stack is larger than a second width of the channel hole at a location of the dielectric layer; forming a channel structure in the channel hole; removing the substrate, the polysilicon layer, and a bottom portion of the channel structure; and forming a semiconductor layer over the channel structure.

14 . The method of claim 13 , wherein forming the stack structure comprising at least the polysilicon layer and the dielectric stack on the substrate, comprises:
forming a p-doping polysilicon layer on the substrate; and performing an NH3 treatment on the p-doped polysilicon layer.

15 . The method of claim 13 , wherein performing the oxidation operation on sidewalls of the channel hole to form the dielectric layer on the polysilicon layer exposed by the channel hole, comprises:
performing a wet oxidation operation on sidewalls of the channel hole.

16 . The method of claim 13 , wherein forming the channel structure in the channel hole, comprises:
forming a memory film over the sidewalls of the channel hole; and forming a semiconductor channel over the memory film above the polysilicon layer.

17 . The method of claim 14 , wherein forming the stack structure comprising at least the polysilicon layer and the dielectric stack on the substrate, comprises:
forming a first dielectric layer on the substrate; forming an undoped polysilicon layer or a carbon-doping polysilicon layer on the first dielectric layer as a first polysilicon layer; and forming the p-doping polysilicon layer on the undoped polysilicon layer or the carbon-doping polysilicon layer as a second polysilicon layer, wherein the first polysilicon layer and the second polysilicon layer are formed in a same deposition operation.

18 . The method of claim 17 , further comprising:
forming a second dielectric layer and a third polysilicon layer on the second polysilicon layer.

19 . The method of claim 18 , wherein forming the channel hole penetrating the stack structure, comprises:
forming the channel hole penetrating the dielectric stack, the third polysilicon layer, the second dielectric layer, the second polysilicon layer, the first polysilicon layer, and the first dielectric layer to expose the substrate.

20 . The method of claim 18 , wherein performing the oxidation operation on sidewalls of the channel hole to form the dielectric layer on the polysilicon layer exposed by the channel hole, comprises:
forming the dielectric layer on the first polysilicon layer and the second polysilicon layer exposed by the channel hole.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Linchun
• Wu Shuangshuang
• Li Lei
• Zhang Kun
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title