Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-11715666-B2
Application number	US-202217574665-A
Country	US
Kind code	B2
Filing date	Jan 13, 2022
Priority date	Jun 21, 2019
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a trench in a semiconductor substrate such that the trench defines an active region;
performing a deposition process at a first temperature range to form an amorphous silicon layer on a surface of the semiconductor substrate in which the trench is formed;
performing a crystallization process on the amorphous silicon layer at a second temperature range to form a polycrystalline silicon layer, the second temperature range being different from the first temperature range;
performing an oxidation process on a surface of the polycrystalline silicon layer to form a silicon oxide layer; and
forming a buried dielectric pattern to fill remaining parts of the trench in which the polycrystalline silicon layer and the silicon oxide layer have been formed.

2. The method as claimed in claim 1 , wherein the first temperature range is lower than the second temperature range.

3. The method as claimed in claim 1 , wherein the silicon oxide layer is thicker than the polycrystalline silicon layer when measured in a same direction.

4. The method as claimed in claim 1 , wherein an interface between the silicon oxide layer and the polycrystalline silicon layer has a surface roughness of 0.1 Å to 10 Å.

5. The method as claimed in claim 1 , wherein:
the semiconductor substrate includes a single crystalline silicon substrate, and
the polycrystalline silicon layer is in direct contact with the single crystalline silicon substrate.

6. The method as claimed in claim 1 , wherein:
the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and
a surface roughness of the second surface is substantially the same as a surface roughness of the first surface.

7. The method as claimed in claim 1 , wherein, during the crystallization process, one or more of O 2 , Ar, N 2 , N 2 O, and H 2 are provided on a surface of the amorphous silicon layer.

8. The method as claimed in claim 1 , wherein the crystallization process and the oxidation process are performed in-situ.

9. The method as claimed in claim 1 , wherein a discontinuous native oxide layer is locally formed between the polycrystalline silicon layer and the semiconductor substrate.

10. The method as claimed in claim 1 , wherein the crystallization process includes allowing a surface of the amorphous silicon layer to adsorb an element for preventing migration of grain.

11. A method of fabricating a semiconductor device, the method comprising:
forming a trench in a semiconductor substrate such that the trench defines an active region;
forming a polycrystalline silicon liner on an inner wall of the trench and a top surface of the semiconductor substrate;
forming a silicon oxide liner on the polycrystalline silicon liner; and
forming a buried dielectric pattern to fill the trench including the polycrystalline silicon liner and the silicon oxide liner,
wherein the polycrystalline silicon liner has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide liner,
wherein the second surface includes a plurality of silicon grains that are uniformly distributed, and
wherein the polycrystalline silicon liner is formed by:
performing a deposition process at a first temperature range to form an amorphous silicon liner on the inner wall of the trench and the top surface of the semiconductor substrate; and
performing a rapid thermal annealing process on the amorphous silicon liner at a second temperature range to form the polycrystalline silicon liner, the second temperature range being different from the first temperature range.

12. The method as claimed in claim 11 , wherein the rapid thermal annealing process includes providing H 2 O, O 2 , O 3 , or oxygen radicals on a surface of the amorphous silicon liner.

13. The method as claimed in claim 11 , wherein the silicon oxide liner is thicker than the polycrystalline silicon liner when measured in a same direction.

14. The method as claimed in claim 11 , wherein the polycrystalline silicon liner has a first thickness on the inner wall of the trench and a second thickness on the top surface of the semiconductor substrate, the second thickness being different from the first thickness.

15. The method as claimed in claim 11 , wherein:
the semiconductor substrate comprises a single crystalline silicon substrate, and
the polycrystalline silicon liner is in direct contact with the single crystalline silicon substrate.

16. A method of fabricating a semiconductor device, the method comprising:
forming a trench in a semiconductor substrate such that the trench defines an active region;
forming a buried dielectric pattern in the trench;
forming a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench;
forming a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench;
forming a gate conductive pattern that is in the semiconductor substrate and runs across the active region;
forming a gate dielectric layer between the semiconductor substrate and the gate conductive pattern; and
forming a plurality of impurity regions in the active region on opposite sides of the gate conductive pattern,
wherein the polycrystalline silicon layer has a first surface in contact with the silicon oxide layer, and
wherein the first surface includes a plurality of silicon grains that are uniformly distributed, and
wherein the polycrystalline silicon layer is formed by:
performing a deposition process at a first temperature range to form an amorphous silicon layer on a surface of the semiconductor substrate including directly on inner walls of the trench; and
performing a rapid thermal annealing process on the amorphous silicon layer at a second temperature range while providing H 2 O, O 2 , O 3 , or oxygen radicals on a surface of the amorphous silicon layer to form the polycrystalline silicon layer, the second temperature range being different from the first temperature range.

17. The method as claimed in claim 16 , wherein the first temperature range is lower than the second temperature range.

18. The method as claimed in claim 16 , wherein the polycrystalline silicon layer is in contact with a bottom surface of the trench and a portion of a lateral surface of the trench.

19. The method as claimed in claim 16 , wherein the gate dielectric layer is in contact with a portion of the polycrystalline silicon layer and a portion of the silicon oxide layer.

20. The method as claimed in claim 16 , wherein the polycrystalline silicon layer has a first thickness on a sidewall of the trench and a second thickness on a top surface of the semiconductor substrate, the second thickness being different from the first thickness.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Im Dong-Hyun
• Lee Kibum
• Kim Daehyun
• We Ju Hyung
• Yoon Sungmi

Classifications

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title