Memory access device and operating method thereof

Patent metadata

Field	Value
Publication number	US-12596649-B2
Application number	US-202519260222-A
Country	US
Kind code	B2
Filing date	Jul 3, 2025
Priority date	Jan 6, 2023
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

Provided is an operating method of a memory access device, the operating method including allowing an access of a first processing element to a plurality of data lines of a memory based on a first command, identifying a number of accesses of the first processing element to the plurality of data lines, and when a number of accesses of the first processing element to a first data line among the plurality of data lines reaches a predetermined number of accesses, allowing an access of a second processing element to the first data line based on a second command.

First claim

The invention claimed is:

1 . An operating method of a memory access device, the operating method comprising:
allowing an access of a first processing element to a plurality of data lines of a memory based on a first command; identifying a number of accesses of the first processing element to the plurality of data lines; and when a number of accesses of the first processing element to a first data line among the plurality of data lines reaches a predetermined number of accesses, allowing an access of a second processing element to the first data line based on a second command, wherein the allowing of the access of the first processing element comprises: storing first data of an external memory in the plurality of data lines based on the first command; and allowing an access of the first processing element to the plurality of data lines in which the first data is stored, and wherein the allowing of the access of the second processing element comprises: when the number of accesses of the first processing element to the first data line among the plurality of data lines reaches the predetermined number of accesses, storing a portion of data among second data of the external memory in the first data line based on the second command; and allowing an access of the second processing element to the first data line in which the portion of data is stored.

2 . The operating method of claim 1 , further comprising when a number of accesses of the first processing element to a second data line among the plurality of data lines reaches the predetermined number of accesses, allowing an access of the second processing element to the second data line based on the second command.

3 . The operating method of claim 1 , wherein the memory comprises:
the plurality of data lines; and a first tag area and a second tag area storing information corresponding to each of the plurality of data lines, wherein the first tag area stores information indicating whether to allow an access of a processing element for each data line, wherein the second tag area stores information indicating a number of accesses of a processing element for each data line, wherein the allowing of the access of the first processing element comprises: allowing the access of the first processing element to the plurality of data lines by changing information of the first tag area, and wherein the identifying comprises: identifying the number of accesses of the first processing elements to each of the plurality of data lines by monitoring the second tag area.

4 . The operating method of claim 1 , further comprising:
storing a first data portion of first data of an external memory in a predetermined number of data lines among the plurality of data lines of the memory; allowing an access of a processing element to the predetermined number of data lines; identifying a number of accesses of the processing element to the predetermined number of data lines; and when a number of accesses of the processing element to each of the predetermined number of data lines reaches the predetermined number of accesses, storing a second data portion of the first data of the external memory in the predetermined number of data lines, and allowing the access of the processing element to the predetermined number of data lines.

5 . The operating method of claim 1 , further comprising:
storing a first data portion of first data stored in the plurality of data lines of the memory, in a predetermined number of data lines among a plurality of data lines of an external memory; and when a number of accesses of a processing element to each of the predetermined number of data lines reaches a second predetermined number of accesses, storing a second data portion of the first data in the predetermined number of data lines.

6 . The operating method of claim 1 , wherein the allowing of the access of the second processing element further comprises:
when a number of accesses of the first processing element to a second data line among the plurality of data lines reaches a second predetermined number of accesses, storing another portion of data among the second data of the external memory in the second data line based on the second command; and allowing an access of the second processing element to the second data line in which the another portion of data is stored.

7 . The operating method of claim 1 , wherein the allowing of the access of the first processing element further comprises:
storing a first data portion of the first data of the external memory in a predetermined number of data lines among the plurality of data lines of the memory; allowing an access of the first processing element to the predetermined number of data lines; identifying a number of accesses of the first processing element to the predetermined number of data lines; and when the number of accesses of the first processing element to each of the predetermined number of data lines reaches the predetermined number of accesses, storing a second data portion of the first data in the predetermined number of data lines and allowing the access of the first processing element to the predetermined number of data lines.

8 . The operating method of claim 1 , further comprising:
allowing an access of a processing element to the plurality of data lines of the memory based on a third command; identifying a number of accesses of the processing element to the plurality of data lines; and when a number of accesses of the processing element to the first data line of the plurality of data lines reaches the predetermined number of accesses, storing data stored in the first data line in an external memory.

9 . The operating method of claim 8 , further comprising when a number of accesses of the processing element to a second data line among the plurality of data lines reaches the predetermined number of accesses, storing data stored in the second data line in the external memory.

10 . The operating method of claim 1 , wherein the memory comprises a scratchpad memory.

11 . A non-transitory computer-readable recording medium comprising a program for performing the operating method of claim 1 on a computer.

12 . A memory access device comprising:
a buffer in which a first command and a second command are stored; and a controller that allows an access of a first processing element to a plurality of data lines of a memory based on the first command by storing first data of an external memory in the plurality of data lines based on the first command and allowing an access of the first processing element to the plurality of data lines in which the first data is stored, identifies a number of accesses of the first processing element to the plurality of data lines, and when a number of accesses of the first processing element to a first data line among the plurality of data lines reaches a predetermined number of accesses, allows an access of a second processing element to the first data line based on the second command by storing a portion of data among second data of the external memory in the first data line based on the second command and allowing an access of the second processing element to the first data line in which the portion of data is stored.

13 . An accelerator comprising:
a memory; a first processing element; a second processing element; and a memory access device that allows an access of the first processing element to a plurality of data lines of the memory based on a first command by storing first data of an external memory in the plurality of data lines based on the first command and allowing an access of the first proce

Assignees

• Rebellions Inc

Inventors

• Baek Seungcheol

Classifications

• G06F13/1673 Primary

  using buffers · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title