Data shift apparatuses and methods

Patent metadata

Field	Value
Publication number	US-9761300-B1
Application number	US-201615358673-A
Country	US
Kind code	B1
Filing date	Nov 22, 2016
Priority date	Nov 22, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

The present disclosure includes data shift apparatuses and methods. An example apparatus includes a memory device. The example memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. A first shared input/output (I/O) line is configured to selectably couple a first subset of the plurality of sense lines and a second shared I/O line is configured to selectably couple a second subset of the plurality of sense lines. A shift element is configured to selectably couple the first shared I/O line to the second shared I/O line to enable a data shift operation. A controller is configured to direct selectable coupling of the array, the sensing circuitry, and the shift element to enable a shift of a data value from the first shared I/O line to the second shared I/O line.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory device, comprising:
an array of memory cells;
sensing circuitry coupled to the array via a plurality of sense lines;
a first shared I/O line configured to selectably couple a first subset of the plurality of sense lines and a second shared I/O line configured to selectably couple a second subset of the plurality of sense lines;
a shift element configured to selectably couple the first shared I/O line to the second shared I/O line to enable a data shift operation; and
a controller configured to direct selectable coupling of the array, the sensing circuitry, and the shift element to enable a shift of a data value from the first shared I/O line to the second shared I/O line.

2. The apparatus of claim 1 , wherein the data shift operation comprises:
a plurality of data values each stored in a first portion of a row, as a source location, by a corresponding plurality of memory cells coupled to a corresponding number of sense lines that are selectably coupled to the first shared I/O line;
the shift element coupling the first shared I/O line to the second shared I/O line; and
movement of the plurality of data values to a corresponding plurality of memory cells in a second portion of the row, as a destination location, coupled to a corresponding number of sense lines selectably coupled to the second shared I/O line; and
wherein the data shift operation further comprises a similar data shift operation performed by movement of data values each stored in the second portion of the row to a corresponding plurality of memory cells in a third portion of the row.

3. The apparatus of claim 1 , wherein:
the sensing circuitry comprises a sense amplifier or a compute component coupled to a particular sense line; and
the sensing circuitry is configured to couple a particular subset of sense lines to a particular shared I/O line in order to implement the data shift operation.

4. The apparatus of claim 1 , wherein the sensing circuitry is formed on pitch with complementary sense lines for corresponding complementary memory cells of a dynamic random access memory (DRAM) array.

5. The apparatus of claim 1 , wherein the shift element comprises:
a latch configured to receive a data value via a first shared I/O line and configured to send the data value via a second shared I/O line to perform the data shift operation; and
a select element configured to enable the data value to be selectably received from a particular first shared I/O line and selectably sent to a particular second shared I/O line.

6. The apparatus of claim 5 , wherein the select element comprises:
first select circuitry configured to selectably receive a data value from a source location via the particular first shared I/O line selected from a plurality of shared I/O lines; and
second select circuitry configured to selectably send the data value to a destination location via the particular second shared I/O line selected from the plurality of shared I/O lines.

7. The apparatus of claim 1 , wherein the shift element is circuitry separate from the sensing circuitry.

8. The apparatus of claim 1 , wherein the shift element is formed on pitch with the sense lines and the memory cells of the array.

9. The apparatus of claim 1 , wherein the shift element is:
formed on chip with and on a different plane than the first shared I/O line, the second shared I/O line, and the memory cells of the array; and
further configured to couple the first shared I/O line at a first node and to couple the second shared I/O line at a second node.

10. The apparatus of claim 1 , wherein:
the shift element is further configured to selectably couple the first shared I/O line of the first subset of the plurality of sense lines to the second shared I/O line of the second subset of the plurality of sense lines and to a third shared I/O line of a third subset of the plurality of sense lines; and
the second shared I/O line is offset relative to the first shared I/O line in a direction opposite from an offset of the third shared I/O line relative to the first shared I/O line.

11. An apparatus, comprising:
a memory device, comprising:
an array of memory cells;
sensing circuitry coupled to the array via a plurality of sense lines;
a plurality of shared I/O lines each configured to selectably and bidirectionally move a data value within the array; and
a pair of shift elements comprising a first shift element and a second shift element, wherein each shift element in the pair is configured to:
couple a particular shared I/O line of the respective plurality of shared I/O lines selectably to a first shared I/O line and a second shared I/O line; and
shift the data value from a coupled first shared I/O line, offset in a first direction by a span of shared I/O lines from the particular shared I/O line, to the second shift element coupled to a second shared I/O line offset in a second direction by the span of shared I/O lines from the particular shared I/O line; and

a controller configured to direct selectable coupling of the array, the sensing circuitry, and the first and second shift elements to enable an operation to shift a data value from the first shared I/O line to the second shared I/O line.

12. The apparatus of claim 11 , wherein:
the first shift element is positioned adjacent the first shared I/O line and is configured to:
read the data value from the coupled first shared I/O line offset in the first direction;
write the data value to the second shift element coupled to the second shared I/O line offset in the second direction in order to perform the data shift operation; and

wherein the read operation and the write operation are performed in different clock cycles.

13. The apparatus of claim 11 , wherein:
the span is a same number of shared I/O lines in the first direction and the second direction by which the first shared I/O line and the second shared I/O line are offset from the particular shared I/O line.

14. The apparatus of claim 11 , wherein:
the first shift element is further configured to:
selectably couple the first shared I/O line as a source to shift the data value across the span to the first shift element; and
shift the data value across the span to the second shared I/O line; and

the second shift element is further configured to:
selectably couple the second shared I/O line to receive movement of the data value across the span as a first destination; and
selectably couple a third shared I/O line to shift the data value across the span to a third shift element as a second destination.

15. The apparatus of claim 11 , wherein the memory device further comprises:
a plurality of subarrays in the array of memory cells; and
a plurality of shared I/O lines each configured to selectably and bidirectionally move a data value within and between the respective plurality of subarrays; and
wherein the data shift operation is performed in a first subarray and a data source location and a data destination location are in a second subarray.

16. The apparatus of claim 15 , wherein:
the second subarray is a subarray for the data source location that is different from a subarray for the data destination location.

17. An apparatus, comprising:
a controller coupled to a memory device and configured to direct a data shift operation, wherein the memory device comprises:
an array of memory cells;
sensing circuitry coupled to the array via a plurality of columns of the memory cells, the sensing circuitry including a sense amplifier or a compute compone

Assignees

• Micron Technology Inc

Inventors

• Willcock Jeremiah J

Classifications

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title