Electronic device having scratchpad memory and management method for scratchpad memory

Patent metadata

Field	Value
Publication number	US-9875191-B2
Application number	US-201514940486-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	May 18, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

An electronic device having a scratchpad memory and a management method are provided. A recording circuit records multiple counter values which correspond to entries in a Translation Lookaside Buffer (TLB). A virtual address is matched with a first entry. If a cache miss occurs, the recording circuit updates a first counter value corresponding to the first entry, and determines if the first counter value meets a threshold criterion. If the first counter value meets the threshold criterion, the recording circuit transmits an interrupts signal to a processing unit, and the processing unit moves data into the scratchpad memory. If the first counter value does not meet the threshold criterion, the data is moved into a cache.

First claim

What is claimed is:

1. An electronic device, comprising:
a processing unit;
a translation lookaside buffer (TLB) coupled to the processing unit and having a plurality of entries, wherein the TLB receives a virtual address from the processing unit, the virtual address is matched with a first entry of the entries, and the TLB outputs a physical address according to the virtual address and a physical page number recorded in the first entry;
a redirector coupled to the TLB and receiving the physical address;
a scratchpad memory coupled to the redirector;
a cache coupled to the redirector;
an external memory; and
a recording circuit coupled to the TLB, the cache and the processing unit, and recording a plurality of count values, wherein the count values are respectively corresponding to the entries,
wherein the redirector transmits the physical address to the scratchpad memory or the cache,
wherein if a cache miss occurs when the physical address is transmitted to the cache, the recording circuit updates a first count value of the count values corresponding to the first entry, and determines whether the first count value meets a threshold criterion,
if the first count value meets the threshold criterion, the recording circuit transmits an interrupt signal to the processing unit, and the processing unit moves data corresponding to the physical address to the scratchpad memory,
if the first count value does not meet the threshold criterion, the data corresponding to the physical address is moved to the cache,
wherein the operation of the recording circuit determining whether the first count value meets the threshold criterion comprises:
the recording circuit determines whether the first count value is greater than a threshold; and
if the first count value is greater than the threshold, the recording circuit determines that the first count value meets the threshold criterion,
wherein the processing unit is further configured to execute a threshold adjustment procedure, and the threshold adjustment procedure comprises:
determining whether there is data moved to the scratchpad memory from a first time point to a second time point or not, and whether the scratchpad memory has a free space; and
decreasing the threshold if no data is moved to the scratchpad memory from the first time point to the second time point and the scratchpad memory has the free space,
wherein if the cache miss occurs when the physical address is transmitted to the cache, the processing unit obtains the data corresponding to the physical address from the external memory, and the threshold adjustment procedure further comprises:
obtaining a current external access number which indicates a number of times of accessing the external memory from the first time point to the second time point;
obtaining a previous external access number which indicates a number of times of accessing the external memory from a third time point to the first time point, wherein the third time point precedes the first time point;
determining whether the current external access number is less than the previous external access number;
keeping the threshold unchanged if the current external access number is not less than the previous external access number; and
resetting the count values.

2. The electronic device of claim 1 , wherein the recording circuit comprises:
a plurality of AND gates, wherein a first input terminal of each of the AND gates is coupled to one of the entries, and a second input terminal of each of the AND gates receives a cache miss signal from the cache,
a plurality of counters respectively coupled to output terminals of the AND gates, and recording the count values;
a plurality of comparators, wherein a first input terminal of each of the comparators receives a threshold, and a second input terminal of each of the comparators is coupled to one of the counters;
an OR gate, having a plurality of input terminal respectively coupled to output terminals of the comparators, and an output terminal outputting the interrupt signal.

3. The electronic device of claim 1 , wherein the threshold adjustment procedure further comprises:
determining whether the threshold is greater than a previous threshold if the current external access number is less than the previous external access number;
increasing the threshold if the threshold is greater than the previous threshold; and
decreasing the threshold if the threshold is not greater than the previous threshold.

4. The electronic device of claim 1 , wherein the processing unit executes the threshold adjustment procedure once a predetermined period.

5. The electronic device of claim 1 , wherein when a context switch occurs in the processing unit, the recording circuit resets the count values.

6. The electronic device of claim 1 , wherein the size of the data corresponding to the physical address is the same as the size of a page when the data corresponding to the physical address is moved to the scratchpad memory.

7. A method for managing an electronic device comprising a processing unit, a translation lookaside buffer (TLB), a redirector, a scratchpad memory and a cache, wherein the TLB has a plurality of entries, and a virtual address from the processing unit is matched with a first entry of the entries, and the TLB outputs a physical address according to the virtual address and a physical page number recorded in the first entry, and the redirector transmits the physical address to the scratchpad memory or the cache, and the method comprises:
recording a plurality of count values which are respectively corresponding to the entries;
if a cache miss occurs when the physical address is transmitted to the cache, updating a first count value of the count values corresponding to the first entry, and determining whether the first count value meets a threshold criterion, wherein the determining whether the first count value meets the threshold criterion comprises:
determining whether the first count value is greater than a threshold; and
if the first count value is greater than the threshold, determining that the first count value meets the threshold criterion;
moving data corresponding to the physical address to the scratchpad memory if the first count value meets the threshold criterion;
moving the data corresponding to the physical address to the cache if the first count value does not meet the threshold criterion;
executing a threshold adjustment procedure, wherein the threshold adjustment procedure comprises:
determining whether there is data moved to the scratchpad memory from a first time point to a second time point or not, and whether the scratchpad memory has a free space; and
decreasing the threshold if no data is moved to the scratchpad memory from the first time point to the second time point and the scratchpad memory has the free space; and
if the cache miss occurs when the physical address is transmitted to the cache, obtaining the data corresponding to the physical address from an external memory, wherein the threshold adjustment procedure further comprises:
obtaining a current external access number which indicates a number of times of accessing the external memory from the first time point to the second time point;
obtaining a previous external access number which indicates a number of times of accessing the external memory from a third time point to the first time point, wherein the third time point precedes the first time point;
determining whether the current external access number is less than the previous external access number;
keeping the threshold unchanged if the current external access number is not less than the previous external access number; and
resetting the count values.

Assignees

• Univ Nat Cheng Kung

Inventors

• Chang Ta-Wei
• Lin Ing-Chao
• Su Wen-Yu
• Chien Yu-Shiang

Classifications

• G06F12/1063 Primary

  the data cache being concurrently virtually addressed · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title

• G06F2212/684

  TLB miss handling · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F2212/60

  Details of cache memory · CPC title