Optimizing access to page table entries in processor-based devices

Patent metadata

Field	Value
Publication number	US-11061820-B2
Application number	US-201916556282-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Aug 30, 2019
Publication date	Jul 13, 2021
Grant date	Jul 13, 2021

Abstract

Optimizing access to page table entries in processor-based devices is disclosed. In this regard, an instruction decode stage of an execution pipeline of a processor-based device receives a memory access instruction including a virtual memory address. A page table walker circuit of the processor-based device determines, based on the memory access instruction, a number T of page table walk levels to traverse, where T is greater than zero (0) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address. The page table walker next performs a page table walk of T page table walk levels of the multilevel page table, and identifies a physical memory address corresponding to a page table entry of the Tth page table walk level. The processor-based device then performs a memory access operation indicated by the memory access instruction using the physical memory address.

First claim

What is claimed is:

1. A processor-based device, comprising:
a system memory comprising a multilevel page table comprising a plurality of page tables, each page table comprising a plurality of page table entries; and
a processing element (PE) comprising:
an execution pipeline comprising an instruction decode stage; and
a page table walker circuit;

the PE configured to:
receive, using the instruction decode stage, a memory access instruction comprising a virtual memory address;
determine, using the page table walker circuit based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (0) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address;
perform, using the page table walker circuit based on the virtual memory address, a page table walk of T page table walk levels of the multilevel page table;
identify, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level; and
perform a memory access operation indicated by the memory access instruction using the physical memory address.

2. The processor-based device of claim 1 , wherein:
the memory access instruction further comprises a traverse indicator that indicates the number T of page table walk levels to traverse; and
the PE is configured to determine the number T of page table walk levels to traverse based on the traverse indicator.

3. The processor-based device of claim 1 , wherein:
the multilevel page table is configured to support recursive traversals;
the virtual memory address indicates one or more recursive traversals of the multilevel page table; and
the PE is configured to determine the number T of page table walk levels to traverse based on a count of the one or more recursive traversals indicated by the virtual memory address.

4. The processor-based device of claim 3 , wherein:
the PE further comprises an optimization selection indicator; and
the PE is configured to determine the number T of page table walk levels to traverse based on the count of the one or more recursive traversals indicated by the virtual memory address responsive to the optimization selection indicator being in a set state.

5. The processor-based device of claim 1 , wherein the PE further comprises a translation lookaside buffer (TLB) configured to cache the page table walk of T page table walk levels of the multilevel page table.

6. The processor-based device of claim 1 , wherein:
the memory access instruction comprises a memory load instruction; and
the PE is configured to perform the memory access operation indicated by the memory access instruction using the physical memory address by being configured to return a content of a memory location indicated by the physical memory address.

7. The processor-based device of claim 1 , wherein:
the memory access instruction comprises a memory store instruction;
the memory store instruction further comprises store data; and
the PE is configured to perform the memory access operation indicated by the memory access instruction using the physical memory address by being configured to write the store data to a memory location indicated by the physical memory address.

8. The processor-based device of claim 1 , wherein:
the memory access instruction comprises a memory read/modify/write instruction;
the memory read/modify/write instruction further comprises store data; and
the PE is configured to perform the memory access operation indicated by the memory access instruction using the physical memory address by being configured to:
return a content of a memory location indicated by the physical memory address; and
write the store data to a memory location indicated by the physical memory address.

9. A method for optimizing access to page table entries, comprising:
receiving, by an instruction decode stage of an execution pipeline of a processing element (PE) of a processor-based device, a memory access instruction comprising a virtual memory address;
determining, by a page table walker circuit of the PE based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (0) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address;
performing, by the page table walker circuit of the PE based on the virtual memory address, a page table walk of T page table walk levels of a multilevel page table;
identifying, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level; and
performing a memory access operation indicated by the memory access instruction using the physical memory address.

10. The method of claim 9 , wherein:
the memory access instruction further comprises a traverse indicator that indicates the number T of page table walk levels to traverse; and
determining the number T of page table walk levels to traverse is based on the traverse indicator.

11. The method of claim 9 , wherein:
the multilevel page table is configured to support recursive traversals;
the virtual memory address indicates one or more recursive traversals of the multilevel page table; and
determining the number T of page table walk levels to traverse is based on a count of the one or more recursive traversals indicated by the virtual memory address.

12. The method of claim 11 , wherein determining the number T of page table walk levels to traverse based on the count of the one or more recursive traversals indicated by the virtual memory address is responsive to an optimization selection indicator of the PE being in a set state.

13. The method of claim 9 , further comprising caching, by a translation lookaside buffer (TLB) of the PE, the page table walk of T page table walk levels of the multilevel page table.

14. The method of claim 9 , wherein:
the memory access instruction comprises a memory load instruction; and
performing the memory access operation indicated by the memory access instruction using the physical memory address comprises returning a content of a memory location indicated by the physical memory address.

15. The method of claim 9 , wherein:
the memory access instruction comprises a memory store instruction;
the memory store instruction further comprises store data; and
performing the memory access operation indicated by the memory access instruction using the physical memory address comprises writing the store data to a memory location indicated by the physical memory address.

16. The method of claim 9 , wherein:
the memory access instruction comprises a memory read/modify/write instruction;
the memory read/modify/write instruction further comprises store data; and
performing the memory access operation indicated by the memory access instruction using the physical memory address comprises:
returning a content of a memory location indicated by the physical memory address; and
writing the store data to a memory location indicated by the physical memory address.

17. A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to:
receive a memory access instruction comprising a virtual memory address;
determine, based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (0) and less than or equal to a number of page table walk levels

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Speier Thomas Philip

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F9/3818

  Decoding for concurrent execution · CPC title